Rick Rutter

Sustainable Networking: How ASICS are Improving Power Consumption

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Image of host Rick Rutter in a blue shirt, white background, next to an image of Chang-Wong Hu, also in a blue shirt. He is wearing a headset and appears to be in a lab. The words “News on the Feed” appear in a green text box below their pictures with the sub text: Sustainable Networking: How Asics are Improving Power Consumption. From Systems on a Chip to Systems in a Package.” 

ASIC architecture can improve network efficiency. Here’s how. 

Juniper engineers work on not just designing next generation products, but also designing them with an eye toward efficiency. In this edition of News on the Feed, Juniper’s Chang-Hong Wu discusses his new Day One Green paper on how Juniper has approached ASIC development and where he thinks it’s headed.

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You’ll learn

  • How systems on a chip have changed to systems in a package 

  • How ASICS are improving power consumption and where it’s going in the near future 

  • Why the first thing Juniper engineers look at when designing next generation products is power consumption 

Who is this for?

Network Professionals Business Leaders


Rick Rutter Headshot
Rick Rutter

Guest speakers

Chang-Hong Wu headshot
Chang-Hong Wu
Engineering VP & Fellow, Juniper Networks 


0:00 hi i'm rick rutter with news on the feed

0:02 as the climate continues to warm and our

0:04 dependency on technology grows the need

0:05 for more sustainable networking

0:07 solutions is critical joining me is

0:09 chang hong woo engineering vp and

0:11 juniper fellow who just published the

0:13 first day one green paper in it he

0:15 describes how our days of simply relying

0:17 on moore's law to deliver faster cheaper

0:19 processing power over and we need to

0:22 think differently especially with demand

0:24 for our networks continuing to grow

0:26 so chang hong to understand where we're

0:28 at today can you please take us back to

0:29 the 2010s and describe how we delivered

0:32 gains and performance and efficiency

0:33 back then

0:35 the decade of 2010 really is a

0:38 transition time

0:40 for the semiconductor industry as the

0:42 decade progresses we also notice the as

0:46 we increase the interconnect speed

0:49 the power

0:50 consumed by interconnecting the chips

0:53 the asics themselves are consuming more

0:56 and more percentage of the power of the

0:58 system

0:59 and so

1:00 so we got some innovation to to use uh

1:04 3d memory we are the first one in the

1:05 networking uh industry to do so

1:09 and the serial with the siri interface

1:12 by that we reduce the num the number of

1:15 input and output uh required for the

1:17 asic we're able to

1:18 to integrate uh all of the packet

1:21 folding function on the line car onto a

1:23 single asic

1:25 and that improved the performance

1:29 as well as the power consumption of the

1:30 a6

1:32 by

1:33 three to four times in that in

1:36 in that duration based on like those

1:39 power improvements or efficiency

1:41 improvements

1:42 did something change right do you think

1:44 you were able to continue to get those

1:46 types of improvements using the same

1:49 technology or same processes

1:52 that's a very good question uh rick

1:54 during the second half of the decade of

1:56 2010 um we integrated more and more

2:00 function on the onto the same piece of

2:02 dice same piece of asic

2:05 yes we were able to improve the

2:06 performance of the networking products

2:09 but then

2:10 the die size the size of the chips we

2:12 produce is getting bigger and bigger in

2:15 the process

2:17 we introduce multiple slice

2:19 or or if you will think of it like a

2:21 multi-core cpus putting more and more

2:23 cores on the cpus

2:25 but the the end result is the buy size

2:28 gets bigger and bigger

2:31 by the end of the decade

2:33 many of the chips are actually

2:35 approaching what we call the reticle

2:38 semiconductor reticle limit

2:40 which is about the biggest

2:43 chip we can produce with the with this

2:45 semiconductor equipment

2:47 and in the meantime the number of

2:49 defects on the chip

2:51 is getting

2:53 bigger and bigger so

2:55 the good buys you can get out of the

2:56 wafer is getting smaller and smaller and

2:59 smaller

3:00 and then that impacts the the cost of

3:02 the chips so clearly from both the die

3:06 size increase as well as the cost of the

3:09 chips we cannot

3:10 do this integration forever uh

3:13 we we need to find somewhere uh

3:15 something else to improve uh in the

3:17 future

3:18 got it and so from what i understand in

3:21 reading your paper like this is where we

3:23 come at how

3:24 we need to deliver more than more right

3:28 in that sense of you know the days of of

3:31 just seeing those automatic increases

3:33 and performance and cost are no more so

3:36 we've got to think a little bit

3:37 differently about how we

3:39 innovate in the future correct that's

3:41 right that's right in fact the whole

3:43 semi-conductor industry is

3:46 encountering the same problem i mean you

3:48 can see all the cpu

3:50 manufacturers are doing that as well

3:52 from amd

3:53 to intel

3:55 and to the recently announced apple's m1

3:58 ultra

4:00 they are putting multiple of these dyes

4:03 inside the package

4:04 so you can see the shift of the design

4:07 space right in the earlier decade of

4:10 2010 we put multiple chips together to

4:12 perform a function and then we

4:14 integrated everything on the same die to

4:16 perform the function better but now

4:18 we're actually breaking it up again but

4:20 not in the old way of putting them on

4:23 the on the board

4:24 which consume a lot of power instead we

4:26 are integrating them inside the package

4:29 with the low power interconnects that

4:31 are developing in the industry we're

4:33 able to

4:34 to overcome that the die size limit as

4:37 well as consuming uh

4:40 less amount of power in the process

4:43 that in fact is

4:45 the way we see networking system uh and

4:48 asic design is going to go in the in in

4:50 the near future

4:52 that's awesome so it sounds like we've

4:54 gone from system on a chip to system in

4:57 a package

4:58 that's right and and some people call it

5:00 a sip as ip as in system in package and

5:04 that will take us the integration inside

5:07 a die now is integration inside the

5:09 package

5:10 to take us to be

5:12 better performance and lower power in

5:14 the future and i would imagine

5:17 better performance and lower power

5:18 consumption also equals

5:21 a more sustainable product and product

5:24 as well

5:26 that's correct um

5:28 and we we are working very hard to

5:30 deliver those products in the market and

5:31 we will say more in the coming months or

5:33 how we we're going to accomplish that

5:36 and in terms of the sustainability

5:39 uh currently uh

5:42 the first thing

5:43 when we're designing a next generation

5:45 product look at we look at power

5:48 consumption right before the power

5:50 consumption in a way is a by-product of

5:52 a design improvement but right now is

5:54 actually the first order of business is

5:57 to do

5:59 is to reduce the power

6:00 because our

6:02 power delivery as well as cooling

6:04 ability are all approaching the limit of

6:07 the state-of-the-art

6:10 technology can do so this is very

6:12 important

6:13 and in the meantime when we are focusing

6:15 on power we are delivering a more

6:17 sustainable product for the planet as

6:19 well well listen chiang hong i wanted to

6:22 thank you so much for joining us today

6:24 and for also working so hard to create a

6:26 more sustainable network

6:27 to read ching hong's paper

6:30 please check out the link below and to

6:32 learn more about how juniper is

6:33 addressing climate change visit

6:35 juniper.net

6:37 climate and while you're on the feed

6:39 please take some time to soak up a

6:40 little industry news and knowledge

6:42 thanks again

6:44 thank you

6:50 you

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