Device Interfaces Overview

Physical Part of an Interface Name

The physical part of an interface name identifies the physical device, which corresponds to a single physical network connector.

Note:

The internal management interface is dependent on the Routing Engine. To identify if the Routing Engine is using this type of interface, use the following command:

show interfaces terse

For more information about the Routing Engines that each chassis supports, the first supported release for the Routing Engine in the specified chassis, the management Ethernet interface, and the internal Ethernet interfaces for each Routing Engine, refer to the link titled Supported Routing Engines by Chassis under Related Documentation.

This part of the interface name has the following format:

type is the media type, which identifies the network device that can be one of the following:

• ae—Aggregated Ethernet interface. This is a virtual aggregated link and has a different naming format from most PICs; for more information, see Aggregated Ethernet Interfaces Overview.

• as—Aggregated SONET/SDH interface. This is a virtual aggregated link and has a different naming format from most PICs; for more information, see Configuring Aggregated SONET/SDH Interfaces.

• at—ATM1 or ATM2 intelligent queuing (IQ) interface or a virtual ATM interface on a circuit emulation (CE) interface.

• bcm—The bcm0 internal Ethernet process is supported on specific Routing Engines for various M series and T series routers. For more information, refer to the link titled Supported Routing Engines by Chassis under Related Documentation.

• cau4—Channelized AU-4 IQ interface (configured on the Channelized STM1 IQ or IQE PIC or Channelized OC12 IQ and IQE PICs).

• ce1—Channelized E1 IQ interface (configured on the Channelized E1 IQ PIC or Channelized STM1 IQ or IQE PIC).

• ci—Container interface.

• coc1—Channelized OC1 IQ interface (configured on the Channelized OC12 IQ and IQE or Channelized OC3 IQ and IQE PICs).

• coc3—Channelized OC3 IQ interface (configured on the Channelized OC3 IQ and IQE PICs).

• coc12—Channelized OC12 IQ interface (configured on the Channelized OC12 IQ and IQE PICs).

• coc48—Channelized OC48 interface (configured on the Channelized OC48 and Channelized OC48 IQE PICs).

• cp—Collector interface (configured on the Monitoring Services II PIC).

• cstm1—Channelized STM1 IQ interface (configured on the Channelized STM1 IQ or IQE PIC).

• cstm4—Channelized STM4 IQ interface (configured on the Channelized OC12 IQ and IQE PICs).

• cstm16—Channelized STM16 IQ interface (configured on the Channelized OC48/STM16 and Channelized OC48/STM16 IQE PICs).

• ct1—Channelized T1 IQ interface (configured on the Channelized DS3 IQ and IQE PICs, Channelized OC3 IQ and IQE PICs, Channelized OC12 IQ and IQE PICs, or Channelized T1 IQ PIC).

• ct3—Channelized T3 IQ interface (configured on the Channelized DS3 IQ and IQE PICs, Channelized OC3 IQ and IQE PICs, or Channelized OC12 IQ and IQE PICs).

• demux—Interface that supports logical IP interfaces that use the IP source or destination address to demultiplex received packets. Only one demux interface (demux0) exists per chassis. All demux logical interfaces must be associated with an underlying logical interface.

• dfc—Interface that supports dynamic flow capture processing on T Series or M320 routers containing one or more Monitoring Services III PICs. Dynamic flow capture enables you to capture packet flows on the basis of dynamic filtering criteria. Specifically, you can use this feature to forward passively monitored packet flows that match a particular filter list to one or more destinations using an on-demand control protocol.

• ds—DS0 interface (configured on the Multichannel DS3 PIC, Channelized E1 PIC, Channelized OC3 IQ and IQE PICs, Channelized OC12 IQ and IQE PICs, Channelized DS3 IQ and IQE PICs, Channelized E1 IQ PIC, Channelized STM1 IQ or IQE PIC, or Channelized T1 IQ).

• dsc—Discard interface.

• e1—E1 interface (including channelized STM1-to-E1 interfaces).

• e3—E3 interface (including E3 IQ interfaces).

• em—Management and internal Ethernet interfaces. For M Series routers, MX Series routers, T Series routers, and TX Series routers, you can use the show chassis hardware command to display hardware information about the router, including its Routing Engine model. To determine which management interface is supported on your router and Routing Engine combination, see Understanding Management Ethernet Interfaces and Supported Routing Engines by Router.

• es—Encryption interface.

• et—Ethernet interfaces (10-, 25-, 40-, 50-, 100-, 200-, and 400-Gigabit Ethernet interface).

• fe—Fast Ethernet interface.

• fxp—Management and internal Ethernet interfaces. For M Series routers, MX Series routers, T Series routers, and TX Series routers, you can use the show chassis hardware command to display hardware information about the router, including its Routing Engine model. To determine which management interface is supported on your router and Routing Engine combination, see Understanding Management Ethernet Interfaces and Supported Routing Engines by Router.

• ge—Gigabit Ethernet interface.

  Note:

  • The XENPAK 10-Gigabit Ethernet interface PIC, which is supported only on M series routers, is configured using the ge interface naming convention instead of the xe interface naming convention. Refer to the following show commands for more information:

    show chassis hardware

    show configuration interfaces

  • In MX and SRX Series Firewalls, the 1-Gigabit and 10-Gigabit SFP or SFP+ optical interfaces are always named as xe even if a 1-Gigabit SFP is inserted. However, in EX and QFX series devices, the interface name is shown as ge or xe based on the speed of the optical device inserted.

• gr—Generic routing encapsulation (GRE) tunnel interface.

• gre—Internally generated interface that is configurable only as the control channel for Generalized MPLS (GMPLS). For more information about GMPLS, see the Junos OS MPLS Applications User Guide.

  Note:

  You can configure GRE interfaces (gre-x/y/z) only for GMPLS control channels. GRE interfaces are not supported or configurable for other applications.

• ip—IP-over-IP encapsulation tunnel interface.

• ipip—Internally generated interface that is not configurable.

• ixgbe—The internal Ethernet process ixgbe0 and ixgbe1 are used by the RE-DUO-C2600-16G Routing Engine, which is supported on TX Matrix Plus and PTX5000.

• iw—Logical interfaces associated with the endpoints of Layer 2 circuit and Layer 2 VPN connections (pseudowire stitching Layer 2 VPNs). For more information about VPNs, see the Junos OS VPNs Library for Routing Devices.

• lc—Internally generated interface that is not configurable.

• lo—Loopback interface. The Junos OS automatically configures one loopback interface (lo0). The logical interface lo0.16383 is a nonconfigurable interface for router control traffic.

• ls—Link services interface.

• lsi—Internally generated interface that is not configurable.

• ml—Multilink interface (including Multilink Frame Relay and MLPPP).

• mo—Monitoring services interface (including monitoring services and monitoring services II). The logical interface mo-fpc/pic/port.16383 is an internally generated, nonconfigurable interface for router control traffic.

• ms—Multiservices interface.

• mt—Multicast tunnel interface (internal router interface for VPNs). If your router has a Tunnel PIC, the Junos OS automatically configures one multicast tunnel interface (mt) for each VPN you configure. Although it is not necessary to configure multicast interfaces, you can use the multicast-only statement to configure the unit and family so that the tunnel can transmit and receive multicast traffic only. For more information, see multicast-only.

• mtun—Internally generated interface that is not configurable.

• oc3—OC3 IQ interface (configured on the Channelized OC12 IQ and IQE PICs or Channelized OC3 IQ and IQE PICs).

• pd—Interface on the rendezvous point (RP) that de-encapsulates packets.

• pe—Interface on the first-hop PIM router that encapsulates packets destined for the RP router.

• pimd—Internally generated interface that is not configurable.

• pime—Internally generated interface that is not configurable.

• pip—Provider Instance Port (PIP) interface for EVPNs.

• rlsq—Container interface, numbered from 0 through 127, used to tie the primary and secondary LSQ PICs together in high-availability configurations. Any failure of the primary PIC results in a switch to the secondary PIC, and vice versa.

• rms—Redundant interface for two multiservices interfaces.

• rsp—Redundant virtual interface for the adaptive services interface.

• se—Serial interface (including EIA-530, V.35, and X.21 interfaces).

• si—Services-inline interface, which is hosted on a Trio-based line card.

• so—SONET/SDH interface.

• sp—Adaptive services interface. The logical interface sp-fpc/pic/port.16383 is an internally generated, nonconfigurable interface for router control traffic.

• stm1—STM1 interface (configured on the OC3/STM1 interfaces).

• stm4—STM4 interface (configured on the OC12/STM4 interfaces).

• stm16—STM16 interface (configured on the OC48/STM16 interfaces).

• t1—T1 interface (including channelized DS3-to-DS1 interfaces).

• t3—T3 interface (including channelized OC12-to-DS3 interfaces).

• tap—Internally generated interface that is not configurable.

• umd—USB modem interface.

• vsp—Voice services interface.

• vc4—Virtually concatenated interface.

• vt—Virtual loopback tunnel interface.

• vtep—Virtual tunnel endpoint interface for VXLANS.

• xe—10-Gigabit Ethernet interface. Some older 10-Gigabit Ethernet interfaces use the ge media type (rather than xe) to identify the physical part of the network device.

• xt—Logical interface for Protected System Domains to establish a Layer 2 tunnel connection.

fpc identifies the number of the FPC or DPC card on which the physical interface is located. Specifically, it is the number of the slot in which the card is installed.

M40, M40e, M160, M320, M120, T320, T640, and T1600 routers each have eight FPC slots that are numbered 0 through 7, from left to right as you face the front of the chassis. For information about compatible FPCs and PICs, see the hardware guide for your router.

On PTX1000 routers, the FPC number is always 0.

The M20 router has four FPC slots that are numbered 0 through 3, from top to bottom as you face the front of the chassis. The slot number is printed adjacent to each slot.

MX Series routers support DPCs, FPCs, and Modular Interface Cards (MICs). For information about compatible DPCs, FPCs, PICs, and MICs, see the MX Series Interface Module Reference.

For M5, M7i, M10, and M10i routers, the FPCs are built in to the chassis; you install the PICs in the chassis.

The M5 and M7i routers have space for up to four PICs. The M7i router also comes with an integrated Tunnel PIC, or an optional integrated AS PIC, or an optional integrated MS PIC.

The M10 and M10i routers have space for up to eight PICs.

A routing matrix can have up to 32 FPCs (numbered 0 through 31).

For more information about interface naming for a routing matrix, see Interface Naming for a Routing Matrix Based on a TX Matrix Router.

pic identifies the number of the PIC on which the physical interface is located. Specifically, it is the number of the PIC location on the FPC. The slots in an FPC with four PIC slots are numbered 0 through 3. The slots in an FPC with three PIC slots are numbered 0 through 2. The PIC location is printed on the FPC carrier board. For PICs that occupy more than one PIC slot, the lower PIC slot number identifies the PIC location.

port identifies a specific port on a PIC or DPC. The number of ports varies, depending on the PIC. The port numbers are printed on the PIC.

channel identifies the channel identifier part of the interface name and is required only on channelized interfaces. For channelized interfaces, channel 0 identifies the first channelized interface.

Logical Part of an Interface Name

The logical unit part of the interface name corresponds to the logical unit number. The range of available numbers varies for different interface types.

In the virtual part of the name, a period (.) separates the port and logical unit numbers:

Separators in an Interface Name

There is a separator between each element of an interface name.

In the physical part of the name, a hyphen (-) separates the media type from the FPC number, and a slash (/) separates the FPC, PIC, and port numbers.

In the virtual part of the name, a period (.) separates the channel and logical unit numbers.

A colon (:) separates the physical and virtual parts of the interface name.

Channel Part of an Interface Name

The channel identifier part of the interface name is required only on channelized interfaces. For channelized interfaces, channel 0 identifies the first channelized interface. For channelized IQ and channelized IQE interfaces, channel 1 identifies the first channelized interface. A nonconcatenated (that is, channelized) SONET/SDH OC48 interface has four OC12 channels, numbered 0 through 3.

To determine which types of channelized PICs are currently installed in the router, use the show chassis hardware command from the top level of the CLI. Channelized IQ and IQE PICs are listed in the output with “intelligent queuing IQ” or “enhanced intelligent queuing IQE” in the description. For more information, see Channelized Interfaces Overview.

For ISDN interfaces, you specify the B-channel in the form bc-pim/0/port:n. In this example, n is the B-channel ID and can be 1 or 2. You specify the D-channel in the form dc-pim/0/port:0.

Note:

For ISDN, the B-channel and D-channel interfaces do not have any configurable parameters. However, when interface statistics are displayed, B-channel and D-channel interfaces have statistical values.

Note:

In the Junos OS implementation, the term logical interfaces generally refers to interfaces you configure by including the unit statement at the [edit interfaces interface-name] hierarchy level. Logical interfaces have the .logical descriptor at the end of the interface name, as in ge-0/0/0.1 or t1-0/0/0:0.1, where the logical unit number is 1.

Although channelized interfaces are generally thought of as logical or virtual, the Junos OS sees T3, T1, and NxDS0 interfaces within a channelized IQ or IQE PIC as physical interfaces. For example, both t3-0/0/0 and t3-0/0/0:1 are treated as physical interfaces by the Junos OS. In contrast, t3-0/0/0.2 and t3-0/0/0:1.2 are considered logical interfaces because they have the .2 at the end of the interface names.

Interface Naming for a Routing Matrix Based on a TX Matrix Router

A routing matrix based on a Juniper Networks TX Matrix router is a multichassis architecture composed of one TX Matrix router and from one to four interconnected T640 routers. From the perspective of the user interface, the routing matrix appears as a single router. The TX Matrix router controls all the T640 routers, as shown in Figure 1.

A TX Matrix router is also referred to as a switch-card chassis (SCC). The CLI uses scc to refer to the TX Matrix router. A T640 router in a routing matrix is also referred to as a line-card chassis (LCC). The CLI uses lcc as a prefix to refer to a specific T640 router.

All LCCs are assigned numbers 0 through 3, depending on the hardware setup and connectivity to the TX Matrix router. For more information, see the TX Matrix Router Hardware Guide. A routing matrix can have up to four T640 routers, and each T640 router has up to eight FPCs. Therefore, the routing matrix as a whole can have up to 32 FPCs (0 through 31).

In the Junos OS CLI, an interface name has the following format:

When you specify the fpc number for a T640 router in a routing matrix, the Junos OS determines which T640 router contains the specified FPC based on the following assignment:

• On LCC 0, FPC hardware slots 0 through 7 are configured as 0 through 7.

• On LCC 1, FPC hardware slots 0 through 7 are configured as 8 through 15.

• On LCC 2, FPC hardware slots 0 through 7 are configured as 16 through 23.

• On LCC 3, FPC hardware slots 0 through 7 are configured as 24 through 31.

For example, the 1 in se-1/0/0 refers to FPC hardware slot 1 on the T640 router labeled lcc0. The 11 in t1-11/2/0 refers to FPC hardware slot 3 on the T640 router labeled lcc1. The 20 in so-20/0/1 refers to FPC hardware slot 4 on the T640 router labeled lcc2. The 31 in t3-31/1/0 refers to FPC hardware slot 7 on the T640 router labeled lcc3.

Table 1 summarizes the FPC numbering for a T640 router in a routing matrix.

Table 1: FPC Numbering for T640 Routers in a Routing Matrix

LCC Numbers Assigned to the T640 Router	Configuration Numbers
0	0 through 7
1	8 through 15
2	16 through 23
3	24 through 31

Table 2 lists each FPC hardware slot and the corresponding configuration numbers for LCCs 0 through 3.

Table 2: One-to-One FPC Numbering for T640 Routers in a Routing Matrix

FPC Numbering	T640 Routers
	LCC 0
Hardware Slots	0	1	2	3	4	5	6	7
Configuration Numbers	0	1	2	3	4	5	6	7
	LCC 1
Hardware Slots	0	1	2	3	4	5	6	7
Configuration Numbers	8	9	10	11	12	13	14	15
	LCC 2
Hardware Slots	0	1	2	3	4	5	6	7
Configuration Numbers	16	17	18	19	20	21	22	23
	LCC 3
Hardware Slots	0	1	2	3	4	5	6	7
Configuration Numbers	24	25	26	27	28	29	30	31

Interface Naming for a Routing Matrix Based on a TX Matrix Plus Router

A routing matrix based on a Juniper Networks TX Matrix Plus Router is a multichassis architecture composed of one TX Matrix Plus router and from one to four interconnected T1600 routers. From the perspective of the user interface, the routing matrix appears as a single router. The TX Matrix Plus router controls all the T1600 routers, as shown in Figure 2.

A TX Matrix Plus router is also referred to as a switch-fabric chassis (SFC). The CLI uses sfc to refer to the TX Matrix Plus router. A T1600 router in a routing matrix is also referred to as a line-card chassis (LCC). The CLI uses lcc as a prefix to refer to a specific T1600 router.

The LCCs are assigned numbers, 0 through 3, depending on the hardware setup and connectivity to the TX Matrix Plus router. For more information, see the TX Matrix Plus Router Hardware Guide. A routing matrix based on a TX Matrix Plus router can have up to four T1600 routers, and each T1600 router has up to eight FPCs. Therefore, the routing matrix as a whole can have up to 32 FPCs (0 through 31).

In the Junos OS CLI, an interface name has the following format:

When you specify the fpc number for a T1600 router in a routing matrix, the Junos OS determines which T1600 router contains the specified FPC based on the following assignment:

• On LCC 0, FPC hardware slots 0 through 7 are configured as 0 through 7.

• On LCC 1, FPC hardware slots 0 through 7 are configured as 8 through 15.

• On LCC 2, FPC hardware slots 0 through 7 are configured as 16 through 23.

• On LCC 3, FPC hardware slots 0 through 7 are configured as 24 through 31.

For example, the 1 in se-1/0/0 refers to FPC hardware slot 1 on the T1600 router labeled lcc0. The 11 in t1-11/2/0 refers to FPC hardware slot 3 on the T1600 router labeled lcc1. The 20 in so-20/0/1 refers to FPC hardware slot 4 on the T1600 router labeled lcc2. The 31 in t3-31/1/0 refers to FPC hardware slot 7 on the T1600 router labeled lcc3.

Table 3 summarizes the FPC numbering for a routing matrix based on a TX Matrix Plus router.

Table 3: FPC Numbering for T1600 Routers in a Routing Matrix

LCC Numbers Assigned to the T1600 Router	Configuration Numbers
0	0 through 7
1	8 through 15
2	16 through 23
3	24 through 31

Table 4 lists each FPC hardware slot and the corresponding configuration numbers for LCCs 0 through 3.

Table 4: One-to-One FPC Numbering for T1600 Routers in a Routing Matrix

FPC Numbering	T1600 Routers
	LCC 0
Hardware Slots	0	1	2	3	4	5	6	7
Configuration Numbers	0	1	2	3	4	5	6	7
	LCC 1
Hardware Slots	0	1	2	3	4	5	6	7
Configuration Numbers	8	9	10	11	12	13	14	15
	LCC 2
Hardware Slots	0	1	2	3	4	5	6	7
Configuration Numbers	16	17	18	19	20	21	22	23
	LCC 3
Hardware Slots	0	1	2	3	4	5	6	7
Configuration Numbers	24	25	26	27	28	29	30	31

Chassis Interface Naming

You configure some PIC properties, such as framing, at the [edit chassis] hierarchy level. Chassis interface naming varies, depending on the routing hardware.

• To configure PIC properties for a standalone router, you must specify the FPC and PIC numbers, as follows:

• To configure PIC properties for a T640 or T1600 router configured in a routing matrix, you must specify the LCC, FPC, and PIC numbers, as follows:

  For the FPC slot in a T640 router in a routing matrix, specify the actual hardware slot number, as labeled on the T640 router chassis. Do not use the corresponding software FPC configuration numbers shown in Table 2.

  For the FPC slot in a T1600 router in a routing matrix, specify the actual hardware slot number, as labeled on the T1600 router chassis. Do not use the corresponding software FPC configuration numbers shown in Table 3.

For more information about the [edit chassis] hierarchy, see the Junos OS Administration Library for Routing Devices.

Examples: Interface Naming

This section provides examples of naming interfaces. For an illustration of where slots, PICs, and ports are located, see Figure 3.

For an FPC in slot 1 with two OC3 SONET/SDH PICs in PIC positions 0 and 1, each PIC with two ports uses the following names:

An OC48 SONET/SDH PIC in slot 1 and in concatenated mode appears as a single FPC with a single PIC, which has a single port. If this interface has a single logical unit, it has the following name:

An OC48 SONET/SDH PIC in slot 1 and in channelized mode has a number for each channel. For example:

For an FPC in slot 1 with a Channelized OC12 PIC in PIC position 2, the DS3 channels have the following names:

For an FPC in slot 1 with four OC12 ATM PICs (the FPC is fully populated), the four PICs, each with a single port and a single logical unit, have the following names:

In a routing matrix on the T640 router labeled lcc1, for an FPC in slot 5 with four SONET OC192 PICs, the four PICs, each with a single port and a single logical unit, have the following names:

For an FPC in slot 1 with one 4-port ISDN BRI interface card, port 4 has the following name:

The first B-channel, the second B-channel, and the control channel have the following names:

Understanding Traditional APS Concept

Traditional Automatic Protection Switching (APS) is configured on two independent physical SONET/SDH interfaces: one interface is configured as the working circuit and the other is configured as the protect circuit (see Figure 4). The circuit, named Circuit X in the figure, is the link between the two SONET interfaces.

Traditional APS uses routing protocols that run on each individual SONET/SDH interface (since circuit is an abstract construct, instead of being an actual interface). When the working link goes down, the APS infrastructure brings up the protect link and its underlying logical interfaces and brings down the working link and its underlying logical interfaces, causing the routing protocols to reconverge. This consumes time and leads to traffic loss even though the APS infrastructure has performed the switch quickly.

Container Interfaces Concept

To solve the problem of traffic loss, the Junos OS provides a soft interface construct called a container interface (see Figure 5).

The container interface allows routing protocols to run on the logical interfaces associated with a virtual container interface instead of on the physical SONET/SDH and ATM interfaces. When APS switches the underlying physical link based on a fault condition, the container interface remains up, and the logical interface on the container interface does not flap. The routing protocols remain unaware of the APS switching.

APS Support for Container-Based Interfaces

With the container interface, APS is configured on the container interface itself. Individual member SONET/SDH and ATM links are either marked as primary (corresponding to the working circuit) or standby (corresponding to the protect circuit) in the configuration. No circuit or group name is specified in the container interface model; physical SONET/SDH and ATM links are put in an APS group by linking them to a single container interface. APS parameters are specified at the container interface level and are propagated to the individual SONET/SDH and ATM links by the APS daemon.

Autocopy of APS Parameters

Typical applications require copying APS parameters from the working circuit to the protect circuit, since most of the parameters must be the same for both circuits. This is automatically done in the container interface. APS parameters are specified only once under the container physical interface configuration and are internally copied over to the individual physical SONET/SDH and ATM links.

T1 and E1 Time-Division Multiplexing (TDM) Interfaces

On the ACX Series routers, existing Junos OS TDM features are supported without changes to statements or functionality. The following key TDM features for T1 (ct1) interfaces and E1 (ce1) interfaces are supported:

• T1 and E1 channelization

• T1 and E1 encapsulation

• Alarms, defects, and statistics

• External and internal loopback

• TDM class of service (CoS)

T1 and E1 mode selection is at the PIC level. To set the T1 or E1 mode at the PIC level, include the framing statement with the t1 or e1 option at the [chassis fpc slot-number pic slot-number] hierarchy level. All ports can be T1 or E1. Mixing T1s and E1s is not supported.

T1 or E1 BITS Interface (ACX2000)

The ACX2000 router has a T1 or E1 building-integrated timing supply (BITS) interface that you can connect to an external clock. After you connect the interface to the external clock, you can configure the BITS interface so that the BITS interface becomes a candidate source for chassis synchronization to the external clock. The frequency of the BITS interface depends on the Synchronous Ethernet equipment client clock (EEC) selected with the network-option statement at the [edit chassis synchronization] hierarchy level.

Note:

The ACX1000 router does not support the BITS interface.

Inverse Multiplexing for ATM (IMA)

Defined by the ATM Forum, IMA specification version 1.1 is a standardized technology used to transport ATM traffic over a bundle of T1 and E1 interfaces, also known as an IMA group. Up to eight links per bundle and 16 bundles per PIC are supported. The following key IMA features are supported:

• IMA Layer 2 encapsulation

• ATM CoS

• ATM policing and shaping

• Denied packets count in the output for the show interfaces at-fpc/pic/port extensive command

Gigabit Ethernet Interfaces

On the ACX Series routers, existing Junos OS Ethernet features are supported without changes to statements or functionality. The following key features are supported:

• Media type specification (ACX1000 router with GbE SFP and RJ45 interfaces)

• Autonegotiation for RJ45 GbE interfaces

• Event handling of SFP insertion and removal

• Explicit disabling of the physical interface

• Flow control

  Note:

  The ACX Series router does not support flow control based on PAUSE frames.

• Loopback

• Loss of signal (LOS) alarm

• Media access control (MAC) layer features

• Maximum transmission unit (MTU)

• Remote fault notification for 10-GbE interfaces

• Statistics collection and handling

• Power over Ethernet (PoE) (ACX2000 router)

• High-power mode

The GbE ports on the router have the capacity to work as a 1-GbE or a 10-GbE interface, depending on the type of small form-factor pluggable (SFP) transceiver inserted. When you insert an SFP+ transceiver, the interface works at the 10-Gigabit speed. When you insert an SFP transceiver, the interface works at the 1-Gigabit speed. Configuration is not required because the speed is determined automatically based on the type of inserted SFP transceiver. The dual-speed interface is automatically created with the xe prefix, such as xe-4/0/0.

The same configuration statements are used for both speeds, and CoS parameters are scaled as a percentage of the port speed. To configure a dual-speed GbE interface, include the interface xe-fpc/pic/port statement at the [edit interfaces] hierarchy level. To display the interface speed and other details, issue the show interfaces command.

Note:

You need to use an industrial-grade SFP below 0dC for ACX 1100 and ACX 2100 boards.