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Jitter Reduction in Hierarchical CoS Queues

Queue Jitter as a Function of the Maximum Number of Queues

Each queuing chip on a Modular Interface Card (MIC) or Modular Port Concentrator (MPC) internally hosts a rate wheel thread that updates the shaper credits into the shapers available at each level of scheduling hierarchy. At each hierarchy level, the length of this update period determines two key characteristics of scheduling:

  • The minimum buffer needed for the queue to pass packets without dropping.

  • The degree of jitter encountered in the queue.

At each hierarchy level, the length of the rate wheel update period is dependent upon the number of entities enabled for that node level. Because traffic is queued at Level 5 (queues) and scheduled upwards to Level 1 (the port), the number of entities (queues) enabled at Level 5 determines the number of entities (logical interfaces, interface-sets, or ports) enabled at the other levels of the scheduling hierarchy. By extension, the number of queues enabled for a given scheduler node hierarchy determines the length of the update period at all hierarchy levels. Consequently, limiting the maximum number of queues supported by a hierarchical queuing MIC or MPC can reduce jitter in the queues. To configure the maximum number of queues allowed per hierarchical queuing MIC or MPC, include the max-queues statement at the [edit chassis fpc slot-number] hierarchy level.

Default Maximum Queues for Hierarchical Queuing MICs and MPCs

The QX chip on a MIC or MPC consists of two symmetrical halves, and each half supports a maximum of 64 K queues (128 K queues per QX chip). The 2-port and 4-port 10-Gigabit Ethernet MICs with XFP and the MPC1_Q line cards have one chipset and can support a maximum of 128 K queues, distributed across the two partitions of the single QX chip. The MPC2 Q and MPC2 EQ line cards have two chipsets and can support a maximum of 256 K queues, distributed across the four partitions of the two QX chips.

Table 1 lists the maximum number of queues supported by default and the corresponding rate wheel update period for each hierarchical queuing MIC or MPC.

Table 1: Default Maximum Queues and Corresponding Rate Wheel Update Periods

Router Model

Hierarchical Queuing MIC or MPC

Maximum Queues

Rate Wheel Update Period

MX5,

MX10,

MX40, and

MX80 modular

2-port 10-Gigabit Ethernet MIC with XFP

The chassis base board hosts one chipset-based Packet Forwarding Engine process that operates in standalone mode. The single QX chip is composed of two partitions that each support 64 K queues for egress ports.

128 K

1.6 ms

MX240,

MX480,

MX960,

MX2010, and

MX2020

MPC1 Q

The MPC1 Q line card hosts one chipset-based Packet Forwarding Engine process that operates in fabric mode. The single QX chip is composed of two partitions that each support 64 K queues for egress ports.

128 K

1.6 ms

MPC2 Q

The MPC2 Q line card hosts two chipset-based Packet Forwarding Engine processes that operate in fabric mode. The two QX chips are composed of four partitions that each support 64 K queues for egress ports.

256 K

1.6 ms

MPC2 EQ

The MPC2 EQ line card hosts two chipset-based Packet Forwarding Engine processes that operate in fabric mode. The two QX chips are composed of four partitions that each support 64 K queues for egress ports.

256 K

2.6 ms

You can configure hierarchical queuing MICs and MPCs to support a reduced maximum number of queues. Doing so reduces the rate wheel update period used by the QX chip, which in turn reduces jitter in the queues for the egress interfaces hosted on the line card.

Shaping Rate Granularity as a Function of the Rate Wheel Update Period

Reducing the length of the QX chip rate wheel update period, in addition to reducing jitter in the hierarchical scheduling queues, also indirectly increases the shaping granularity.

For a given port line rate and scheduling hierarchy level, the shaping granularity is a function of the minimum shaper credit size and the rate wheel update period in effect as a result of the number of queues supported by the line card.

Table 2 shows how shaping granularity is calculated for non-enhanced hierarchical queuing MIC and MPC line cards with default values for minimum shaper credit size and for rate wheel update period.

Table 2: Default Shaping Granularities on Non-Enhanced Queuing MICs and MPCs

Port Type

Hierarchy Level

Non-Enhanced Queuing MIC or MPC Defaults

Calculation of Shaping Granularity

Minimum Credit

Update Period

 1 Gbps Queuing

Level 1 (port), Level 4 (queues)

 4 bytes  =   32 bits

13.33 ms  =  0.01333 sec

 32 bits  /  0.01333 sec  =    2.4 Kbps

Level 2, Level 3

16 bytes  =  128 bits

 1.66 ms  =  0.00166 sec

128 bits  /  0.01333 sec  =   9.6 Kbps

10 Gbps Queuing

Level 1 (port), Level 4 (queues)

16 bytes  =  128 bits

13.33 ms  =  0.01333 sec

128 bits  /  0.01333 sec  =   9.6 Kbps

Level 2, Level 3

64 bytes  =  512 bits

 1.66 ms  =  0.00166 sec

512 bits  /  0.01333 sec  =  38.4 Kbps