Channelization on the PTX10002-60MR

You can split the high-speed ports on your device into multiple low-speed ports using channelization.

Channelization is the architectural capability to subdivide a single high-capacity physical port into multiple independent, lower-speed logical interfaces allowing operators to maximize hardware port utilization. You use a breakout cable if your goal is to maximize port density by splitting a single physical high-speed port into multiple distinct, lower-speed devices (like servers, firewall interfaces, or top-of-rack switches). You should insert a standalone lower-speed transceiver if your goal is a point-to-point connection to a single legacy device.

Note:

To channelize ports, you must initially configure them to operate at the required speed. See Configure Port Speeds for Channelized Interfaces.

To check port speeds, see port checker.

Channelization into 4x25-Gbps, 4x10-Gbps, and 1x40-Gbps interfaces is only allowed on ports 0, 4, 8, 12 ,16, 20, 24-35, 36, 40, 44, 48, 52, 56. When P0 is channelized, ports 1, 2, and 3 must be unused. This guideline must be followed because a channelized port, for example, port X, would consume the resources and lanes that are required for the ports X+1, X+2, and X+3.

The associated interfaces in Junos OS Evolved follow this naming convention (where x represents physical port number, y represents sub port number)

• Non-channelized interface:et-0/0/x

• Channelized interface:et-0/0/x:y

These ports have the following default speeds:

• Ports 0–23 and 36–59 housing QSFP28 transceivers support 100 Gbps

• Ports 24–35 housing QSFP112-DD transceivers support 800 Gbps

The following table shows the supported speeds on the 48 QSFP28 Ports in the PTX10002-60MR router.

Table 1: PTX10002-60MR—Port Speed Capabilities for QSFP28 Ports

	Ports
	0, 8, 16, 36, 44, 52	1, 9, 17, 37, 45, 53	2, 10, 18, 38, 46, 54	3, 11, 19, 39, 47, 55	4, 12, 20, 40, 48, 56	5, 13, 21, 41, 49, 57	6, 14, 22, 42, 50, 58	7, 15, 43, 51, 59
Interface speeds	100	100	100	100	100	100	100	100
	2x50	—	—	2x50	2x50	—	—	2x50
	4x25	—	—	—	4x25	—	—	—
	40	—	—	—	40	—	—	—
	4x10	—	—	—	4x10	—	—	—
	10	10	10	10	10	10	10	10
ZR Optics Support	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes

Note:

The QSFP28 ports support the QSA adaptor - which can support native 10 Gbps optics.

Note:

When port x is channelized into n IFDs, then ports x+1 to ports x+n-1 must be explicitly marked as unused. For example, E.g. if port 0 is configured as 4x25 GbE, then ports 1, 2, 3 must be marked as unused.

Breakout modes of 4x10GbE and 4x25GbE and an unchannelized 40GbE port are supported only on every fourth alternate QSFP28 port starting from port 0. Therefore, when you channelize a QSFP28 port, you must leave the subsequent three ports unused. You can leave these ports unconfigured or configure them as unused. Any subsequent configurations on these ports will result in commit failure.

The breakout mode of 2x50GbE is supported only on the topmost and bottommost ports and you must explicitly mark the corresponding adjacent port (X+1 for topmost and X-1 for bottommost port) as unused. Any subsequent configurations on the adjacent port will result in commit failure.

When you configure port X as 40GbE, you must explicitly mark ports X+1 through X+3 as unused. For example, if port 20 is configured as 40GbE, then ports 21, 22, and 23 must be marked as unused.

All QSFP28 ports support 100GbE and 10GbE.

The following table describes the supported speeds on the 12 QSFP112-DD ports in PTX10002-60MR.

Table 2: PTX10002-60MR—Port Speed Capabilities for QSFP112-DD Ports

	Speeds (Gbps)	Ports
		24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35
Interface Speeds	800	8 x 100 Gbps
		2 x 400 Gbps
		1 x 800 Gbps
	400	4 x 100 Gbps
		2 x 200 Gbps
		1 x 400 Gbps
	200	2 x 100 Gbps 4 x 200 Gbps
	100	100 Gbps
	50	8 x 50 Gbps
	25	4 x 25 Gbps
	10	4 x 10 Gbps
ZR Optics support		Yes

Note:

QSFP112-DD ports do not have any constraints and will support all speeds and channelization.

Note:

ZR/ZR+ optics support:

• Supported on all 48 QSFP28 ports.

• Supported on all 12 QSFP112-DD ports.