Know Your 400G Transceiver

Key Characteristics

The following are the key design considerations for an 400G transceiver:

• Form Factor—Juniper's 400G optical transceivers incorporate the Quad Small Form-factor Pluggable Double Density (QSFP-DD) form factor to meet high power and thermal requirements for 400 Gbps data transmission. QSFP-DD is the dominant form factor for 400G optics in the industry.

  Note:

  For 400G optical transceivers, Juniper does not currently support the OSFP form factor.

• Fiber type and reach—The fiber type specifies the type of optical fiber (single-mode or multimode) compatible with 400G transceivers. The reach provides the maximum supported distance or range for an optical transceiver. It helps you to select the appropriate optical transceiver for different applications, such as inter-data center, intra-data center, long-haul networks, and so on.

• Lane Distribution—IEEE 802.3ba defines lane distribution. Lane distribution happens in the PCS, and lanes are then multiplexed to 1, 4 or 8 lanes in the PMD depending on the exact optics type. The types of lane distribution include:

  • Single lane—In a single-lane configuration, the entire Ethernet signal is conveyed through one optical lane or channel.

  • Multiple lanes—Multiple lane distribution leverages parallel optical transmission by stripping Ethernet signals into multiple low rate lanes. The low rate lanes map into optical lanes or channels. This results in a more optimal cost per bit, fewer points of failure and interfaces, and lower power and heating.

  400G optics support only the 400G lane rate. However, with breakout, Juniper's 400G optics can be split into multiple sub-interfaces, ensuring that the total bandwidth is 400G. The breakout ports of lower speeds are fully independent and can run on separate time domains, enabling higher density applications.

  Figure 3: 4x100G Solution Using Four Wavelengths

Juniper Optical Product Numbers

Juniper's optical components such as transceivers, cables, and connectors follow a naming convention. Each element in the product name corresponds to a specification. It helps you to better understand and select the optical component that you need. For example:

• JCO400-QDD-ZR

  • JCO—It denotes Juniper coherent optical (JCO) transceivers or tunable DWDM optical transceivers. JCO is a core component of the Juniper Converged Optical Routing Architecture (CORA). It offers industry-leading power efficiency, operational simplicity, an open architecture, and an integrated DWDM design. The 400 in JCO400 indicates that the transceiver is capable of handling transmission speeds of 400 Gbps.

  • QDD—Short for QSFP-DD. It identifies the form-factor of the transceiver.

  • ZR—ZR is a standard developed by the Optical Internetworking Forum (OIF). It is offered in either ZR and ZR+ specifications. JCO400-QDD-ZR supports ZR that is capable of transmitting data over distances of up to 120 kilometers.

• QDD-400G-DR4

  • QDD—Short for QSFP-DD. It identifies the form-factor of the transceiver.

  • 400G—Indicates that the transceiver is capable of data transfer rates of 400 Gbps.

  • DR4—Stands for 400GBase-DR4. It is a specific standard that uses four parallel lanes of 100 Gbps to deliver 400 Gbps.

400G (X8) Transceiver Architecture

The industry-standard and most widely deployed design for 400G transceivers uses an eight-lane 8x50G PAM4 electrical interface (400GAUI-8) on the host side. X8 denotes the eight-lane electrical interface. The host side represents the part of the transceiver that connects to the switch, router, or any other host device. On the line side, the 400G transceivers uses a four-lane 4x100G PAM4 optical interface (400G-DR4). The line side represents the part of the transceiver that transmits and receives data over fiber cables to the network.

This architecture is used in 400G transceiver form factors like QSFP-DD. The following are the different components of a 400G transceiver architecture:

• 400G platform—The Juniper device (switch or router) that supports the 400G architecture.

• 8x50 Gbps electrical—The electrical interface between the switch and the transceiver components. It can transmit data over eight separate 50 Gbps electrical lanes.

• 4x100 Gbps optical—The optical interface between the transceiver and the network. It can transmit data over four separate 100 Gbps optical lanes.

• Digital Signal Processor (DSP)—The 400G DSP (Digital Signal Processor) performs signal conditioning and conversion between the 8x50G electrical lanes and the 4x100G optical lanes. PAM4 effectively doubles the amount of data that you can transmit. The CDR is responsible for re-timing incoming data to reduce jitter. The DSP handles functions like equalization, error correction, and other signal processing tasks.

• Driver—Drivers are electronic components that amplify the electrical signal. The x8 transceiver architecture has eight drivers. Each driver corresponds to a 50G lane.

• Directly modulated lasers—Modulated lasers convert the amplified electrical signals into optical signals. It includes Vertical-Cavity Surface-Emitting Lasers (VCSELs) for multimode applications and Directly Modulated Lasers (DMLs) for single-mode applications.

• Transimpedance Amplifiers (TIA)—TIA is the receiving end of an optical transmission. It converts the electrical current output of a photodiode to a specific voltage level. It can operate with very low signal levels that are typical for long-distance optical communication.

• Photo-Detector—It works in tandem with the TIA to convert the optical information back into electrical form.

Some 400G optical transceivers, such as SR8 modules, use eight parallel lanes each running at 50G PAM4, directly converting electrical to optical signals. Some 400G optical transceivers use a gearbox to convert 8×50G electrical lanes into 4×100G optical lanes. For example, FR4 and LR4 modules use an 8:4 gearbox, where the eight electrical lanes at 50G PAM4 are converted into four optical lanes at 100G PAM4. This reduces the number of optical lanes and fibers required, simplifying cabling and connectors. For example, an 8×100G architecture requires eight fibers for its eight lanes, often using MPO connectors or multiple duplex LC connectors. However, a 400G module such as FR4 or LR4 that uses 4×100G optical lanes requires only four fibers (two duplex LC connectors) to transmit and receive signals.

Serializer/Deserializer (SerDes)

A SerDes consists of an integrated circuit (IC or chip) transceiver. An IC can hold multiple SerDes. Each SerDes within an IC can have multiple lanes. Each of these lanes in a SerDes can handle input and output traffic. The two functional units or blocks within a SerDes are:

• Parallel in serial out (PISO) or the Serializer—Converts parallel data into serial data. The transmitter section of the transceiver functions as a parallel-to-serial converter that converts parallel data to serial data.

• Serial in parallel out (SIPO) or the Deserializer—Converts serial data into parallel data. The receiver section of the transceiver serves as a serial-to-parallel converter that converts the serial data back to parallel data.

SerDes devices support multiple operational modes between two points:

• Simplex operations—Allows data conversion to occur only in one direction.

• Full-duplex operations—Allows data conversion to occur in both directions simultaneously.

• Half-duplex operations—Allows data conversion to occur in both directions, but not simultaneously.

Figure 4: Transmission Modes in SerDes Devices

SerDes reduces the number of data paths and connecting pins or wires needed to transmit data. It counters the common issues associated with parallel power transmission such as increased power consumption, electromagnetic interference, and clock timing errors. Using SerDes, you can efficiently transmit the data signals from a port through its multiple breakout channels into the optic network and vice versa.

Figure 5: Data Exchange in SerDes Chips