Configuring Transparent Encoding for CTP Bundles (CTPView)
This topic describes how to configure transparent encoding for CTP bundles. You must configure transparent encoding on each end of the circuit.
To reduce transport latency, we recommend that you use the smallest buffer values possible for networks.
There are two modes of transparent encoding. They are Transparent 4 mode (TRANS) and Transparent 8 mode (TRANS8). TRANS8 mode is supported only on CTPOS Release 6.4 and later. It is not supported on CTPView. After you configure TRANS8 from CTPOS, you cannot reconfigure the bundle from CTPView.
This topic describes how to configure the TRANS encoding.
Before you begin:
Log in to the CTPView software at least at the Net_Admin level.
Connect the CTPView server to the CTP device for which you want to configure bundles.
To configure transparent encoding parameters for CTP bundles using CTPView:
- In the side pane, select Bundle > Configuration.
- Run your mouse over the Display and Select an Existing Bundle bar.
- In the table of bundles, select the bundle that you want to modify.
- Under Port Options, set Serial Encoding to TRANS.
- Configure the Port Speed and Clock Cfg as described in Table 21.
- Under Port Options, select Advanced Options Show to display advanced parameters and configure the parameters as described in Table 21.
- Click Click to Submit Bundle AND Port Changes.
Table 21: CTP Bundle Transparent Encoding Parameter Settings in CTPView
Specifies the sample rate for user data. The port rate should be a multiple of the user data rate.
Enter a number from 0.00100 through 12880.00000 KHz.
Specifies the clocking method used for the transparent circuit.
To prevent errors in transport, both ends of a circuit must be synchronized with each other. You can accomplish this by either locking each end of the circuit to a common reference or by enabling adaptive clocking at one end of a circuit.
16-Bit Jitter Absorption FIFO
Enables or disables the phase correction FIFO buffer. This FIFO buffer aligns the clock and data phase relationship on a TRANS encoded circuit in which the clock travels in one direction and the data travels in the opposite direction.
Enable this FIFO buffer at one end of the circuit, but not at both ends.
Invert FIFO Write Clock
Specifies whether or not to invert the FIFO buffer write clock.
Invert FIFO Read Clock
Specifies whether or not to invert the FIFO read clock.
Use ST Lead (instead of RTS/CTS)
Specifies that the circuit uses the ST lead instead of the RTS and CTS leads to sample local SD/TT/RTS/DTR signals and forward them to the remote RD/RT/CTS/DSR signals.
The RTS and DTR signals are subject to additional delay and jitter because they are signaling leads. On higher-speed circuits, the delay and jitter on these paths make the signal choices nonoptimal. Therefore, you can specify that the circuit uses the ST lead instead of the RTS and CTS leads, which will not have this delay and jitter.