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PHY Timestamping

SUMMARY The PHY timestamping refers to the timestamping of the IEEE 1588 event packets at the 1-Gigabit Ethernet and 10-Gigabit Ethernet PHY. Timestamping the packet in the PHY results in higher stability of recovered clock.

PHY Timestamping

Juniper Networks recommends that you configure timestamping at the physical layer if the port supports IEEE 1588 timestamping.

The PHY timestamping on ACX updates the correction field of the packet. ACX supports PHY timestamping in ordinary clock and boundary clock modes.

On 10-Gigabit Ethernet ports, PHY timestamping and WAN-PHY framing are mutually exclusive—that is, you cannot configure PHY timestamping on a 10-Gigabit Ethernet port if you have configured WAN-PHY framing mode on that port. This is applicable only for MPC5E and MPC6E with 24x10XGE MIC. PHY timestamping is not supported on the enhanced MPCs MPC1E, MPC2E, and MPC4E. Only hardware timestamping is supported on these MPCs. Therefore, a packet delay variation (also known as jitter) of up to 1 microsecond is observed on these MPCs for a very small percentage of packets occasionally. Hardware timestamping is typically timestamping either at FPGA or similar device.

On Junos EVO platforms, PHY timestamping is enabled by default and the phy-timestamping configuration option is unavailable.

Configure PHY Timestamping

You can configure timestamping either at the physical layer or at the nonphysical layer on the 10-Gigabit Ethernet and 100-Gigabit Ethernet ports. The PHY timestamping on ACX updates the correction field of the packet. ACX supports PHY timestamping in ordinary clock and boundary clock modes.

Note:

PHY timestamping is supported only on ACX500 line of routers.

The following points need to be considered while configuring PHY timestamping in ACX routers:

  • PHY timestamping is enabled or disabled on all the PHYs. You cannot selectively enable or disable PHY timestamping on a particular interface.

  • When PHY timestamping is enabled, the transparent clock functionality is also enabled.

Note:

The PHYs on ACX do not support transparent clock functionality for PTP-over-MPLS. You should not enable transparent clock or PHY timestamping if PTP is transported over MPLS.

In ACX2000 router, the transparent clock operation is not supported on the 10-Gigabit Ethernet port.

To enable PHY timestamping on ACX routers, configure clock-mode (ordinary clock or boundary clock) along with the transparent-clock CLI statement at the [edit protocols ptp] hierarchy.

Note:

Starting in Junos OS Release 17.1 onwards, to configure transparent clock, include the e2e-transparent CLI command at the [edit protocols ptp] hierarchy level. Prior to Junos OS Release 17.1, to configure transparent clock, include the transparent-clock CLI command at the [edit protocols ptp] hierarchy level.

Enable PHY Timestamping for Ordinary Clock Member

The following procedure enables you to configure PHY timestamping for ordinary clock client in ACX:

  1. Configure the clock mode as ordinary.
  2. Configure the transparent clock.
  3. Configure the interface for client clock.

Enable PHY Timestamping for Boundary Clock

The following procedure enables you to configure PHY timestamping for boundary clock in ACX:

Note:

PHY timestamping is supported only on ACX500 line of routers.
  1. Configure the clock mode as boundary.
  2. Configure the transparent clock.
  3. Configure the interface for client clock.
  4. Configure the interface for primary clock.

Enable PHY Timestamping for Reference Clock

The following procedure enables you to configure PHY timestamping for reference clock in ACX:

Note:

In ACX Series routers, the reference clock functionality is supported only on ACX500 router.
  1. Configure the clock mode as ordinary.
  2. Configure the transparent clock.
  3. Configure the interface for primary clock.

Configure PHY Timestamping on ACX2200 Routers

The PHY timestamping refers to the timestamping of the IEEE 1588 event packets at the 1-Gigabit Ethernet and 10-Gigabit Ethernet PHY. Timestamping the packet in the PHY results in higher stability of recovered clock. The PHY timestamping on ACX updates the correction field of the packet. ACX2200 supports PHY timestamping in boundary clock mode.

The following points need to be considered while configuring PHY timestamping in ACX routers:

  • PHY timestamping is enabled or disabled on all the PHYs. You cannot selectively enable or disable PHY timestamping on a particular interface.

  • When PHY timestamping is enabled, the transparent clock functionality is also enabled.

Note:

The PHYs on ACX do not support transparent clock functionality for PTP-over-MPLS. You should not enable transparent clock or PHY timestamping if PTP is transported over MPLS.

To enable PHY timestamping on ACX2200 routers, configure boundary clock along with e2e-transparent CLI statement at the [edit protocols ptp] hierarchy.

Enable PHY Timestamping for Boundary Clock

The following procedure enables you to configure PHY timestamping for boundary clock in ACX2200 routers:

  1. Configure the clock mode as boundary.
  2. Enable Phy timestamping on boundary clock.
  3. Configure the interface for client clock. For information on configuring PTP client clock interface, see Configure PTP Member Clock.
  4. Configure the interface for primary clock. For information on configuring PTP primary boundary clock, see Configure PTP Primary Boundary Clock.