Configure PHY Timestamping on ACX500 and ACX2K Routers

The PHY timestamping refers to the timestamping of the IEEE 1588 event packets at the 1-Gigabit Ethernet and 10-Gigabit Ethernet PHY. Timestamping the packet in the PHY results in higher stability of recovered clock. The PHY timestamping on ACX updates the correction field of the packet. ACX2200 supports PHY timestamping in boundary clock mode.

The following points need to be considered while configuring PHY timestamping in ACX routers:

• PHY timestamping is enabled or disabled on all the PHYs. You cannot selectively enable or disable PHY timestamping on a particular interface.

• When PHY timestamping is enabled, the transparent clock functionality is also enabled.

Note:

The PHYs on ACX do not support transparent clock functionality for PTP-over-MPLS. You should not enable transparent clock or PHY timestamping if PTP is transported over MPLS.

To enable PHY timestamping on ACX500, ACX2100 and ACX2200 routers, configure boundary clock along with e2e-transparent CLI statement at the [edit protocols ptp] hierarchy.