Help us improve your experience.

Let us know what you think.

Do you have time for a two-minute survey?

 
 

Clock Synchronization

SUMMARY Clock synchronization aims to coordinate otherwise independent clocks.

Clock Synchronization Overview

MX Series and PTX Series routers support external clock synchronization and automatic clock selection for Synchronous Ethernet, T1 or E1 line timing sources, and external inputs.

Configuring external clock synchronization and automatic clock selection requires making clock selection, quality level, and priority considerations. The clock source selection algorithm is used to pick the two best upstream clock sources from among the various sources on the basis of system configuration and execution criteria such as quality level, priority, and hardware restrictions.

You can configure several options for external clock synchronization. For an overview about the configuration options, see Configure Clock Synchronization Interface on MX Series Routers.

MX 10003 routers support external clock synchronization and automatic clock selection for Synchronous Ethernet, T1 or E1 line timing sources, and external inputs.

MX5-T, MX10-T, MX40-T, MX80, MX80-T, MX240, MX480, MX960, MX2020, PTX3000, and PTX5000 routers support external clock synchronization using Synchronous Ethernet. Synchronous Ethernet is a physical layer technology that functions regardless of the network load and supports hop-by-hop frequency transfer, where all interfaces on the trail must support Synchronous Ethernet.

Currently, two types of clocking modes are supported on MX Series routers, the distributing clocking mode and the centralized clocking mode.

The Switch Control Board (SCB) supports distributed clocking mode. The Enhanced Switch Control Board—SCBE—supports centralized clocking mode and has one external clock interface.

The Enhanced Switch Control Board—SCBE2—supports centralized clocking mode and has two external clock interfaces external-0/0 and external-1/0. Note that the external-0/0 interface refers to the external interface on the SCB in slot 0 and the external 1/0 interface refers to the external interface on the SCB slot 1.

On SCBE2, you can configure the external synchronization options only on the external interface on the active SCB. Therefore, if the active SCB is in slot 0, then you can configure the external-0/0 interface only. If the active SCB is in slot 1, then you can configure the external-1/0 interface only.

The PTX Series Packet Transport Routers support an external synchronization interface that can be configured to synchronize the internal Stratum 3 clock on the CCG to an external source, and then synchronize the chassis interface clock to that source.

Clocking Modes, External Clock Synchronization, and Configuration Parameters

The following sections explain clocking modes, external clock synchronization and its configuration parameters in detail:

Distributed Clocking Mode

In the distributing clocking mode, the Switch Control Board (SCB) supports synchronizing the MX Series router’s chassis to an internal Stratum 3 free-run oscillator. The Synchronous Ethernet timing messages are sent through the chassis to support the network timing trails that are traceable to a high-quality timing source. The timing messages are carried through the network by the Ethernet switches that were traditionally handled by time-division multiplexing (TDM) equipment over SONET/SDH interfaces. The distributing clocking mode is handled through ESMC messages. The ESMC support is based on the ITU-G.8264 specification. The ESMC messages transmit the clock quality of the line timing signal in the form of the (Synchronous Status Message) SSM TLV that is carried in the ESMC packet.For more information, see Ethernet Synchronization Message Channel Overview.

The distributed clocking mode has the following limitations:

  • There is no SCB centralized clock module to synchronize the entire chassis.

  • The recovered line timing is driven out only by the line interface of the 16-port 10-Gigabit Ethernet MPC.

  • The distributed mode does not support external clock interface timing.

Centralized clocking mode overcomes these limitations by distributing and driving timing out on all the chassis line interfaces.

Centralized Clocking Mode

The Enhanced SCB SCBE on the MX240, MX480, and MX960 routers supports a Stratum 3 clock module. This clock module functions as a centralized point within the chassis for clock monitoring, filtering, holdover, and selection. It has only one external clock interface.

The Enhanced SCB SCBE2 on the MX240, MX480, and MX960 routers supports two external clock interfaces external-0/0 and external-1/0. The external-0/0 interface refers to the external interface on the SCB in slot 0 and the external 1/0 interface refers to the external interface on the SCB in slot 1.

In SONET/SDH networks, the routers use the best-quality clock available in the network. The quality level of various clock sources in the network is determined by monitoring the Synchronization Status Messages (SSMs) from the clock sources. An SSM occupies a fixed location in the SONET frame. On Ethernet networks that use Synchronous Ethernet for clock synchronization, the SSM is not a part of the timing signal. The SSM is carried in the Ethernet packets that flow in the Ethernet Synchronization Message Channel (ESMC). By interpreting the SSM values, the router determines the clock quality associated with the clock source, and performs its clock selection accordingly. The ESMC messages transmit the clock quality of the line timing signal in the form of the SSM TLV that is part of the ESMC packet.

Note that the clock in the router goes into holdover mode in the absence of any clock sources with best quality level and in turn uses the timing information stored in its buffer to synchronize itself.

The following processes play a crucial role during external synchronization of the clock sources in the control board. Note that PTX Series routers need two best clock sources that act as primary and secondary clock sources, whereas MX Series routers need only one best clock source.

  • The clock sync process (clksyncd) performs the clock selection and participates in ESMC message exchange. For clock selection, in the absence of user-configured primary or secondary clock sources, the clksyncd runs a clock selection algorithm and selects the two best clocks available as the primary and secondary clock sources, respectively, for a PTX Series router or selects a best clock for an MX Series router. The clksyncd also sends out periodic ESMC packets to transmit its clock’s quality level to the other routers in the network—this is specified in the SSM TLV in the ESMC packet—and receives ESMC packets from other clock sources and tracks the received clock signal quality level. ESMC packets are received on all the interfaces that are configured as clock sources. ESMC packets are also transmitted to the clock-source interfaces on other routers, as well as to the interfaces that are configured to receive ESMC packets on other routers.

  • The chassis process (chassisd) is responsible for interfacing with the Enhanced Switch Control Board (SCBE) on MX Series routers and Centralized Clock Generator (CCG) on PTX Series routers. It monitors the clock quality and assists SCBE or the CCG to determine the clock source with the best quality level. When it detects clock quality deterioration, it informs clksyncd to select another primary clock source. After clock selection chassisd is updated with the latest clock source information. Note that in the absence of user-configured primary and secondary clock sources on PTX Series routers, the clock sources are selected through the clock algorithm and chassisd is updated with the latest clock information. Consequently, a new interprocess connection is established between chassisd and clksyncd.

  • The periodic packet management process (ppmd) performs periodic transmission of ESMC packets to others routers in the network. It also receives incoming ESMC packets from other routers. The ppmd filters out repetitive ESMC packets to reduce packet flows between ppmd and clksyncd.

The following explains a simple clock selection process using ESMC packets:

  • The Synchronous Ethernet (line timing) signal is an Ethernet physical layer signal that is received on the Ethernet interface. ESMC is a Layer 2 Ethernet packet. The Synchronous Ethernet signal and the ESMC packets are received on the Ethernet interface of the router.

  • The received Synchronous Ethernet signal is sent to the clock hardware in the SCBE or in the CCG, whereas the ESMC packets—with the quality level—is directed to the clksyncd.

  • The clock selection algorithm in clksyncd selects the best clock signal based on the quality level in the ESMC packet from one of the interfaces that is configured as a clock source. On PTX Series routers, the algorithm also selects the next best—when available—clock as the secondary clock.

  • The best clock information is transmitted to the chassisd, which in turn generates a command to the clock hardware to use the best clock as the reference clock. On PTX Series routers, both primary and secondary clocks are used..

  • The reference clock uses the best—primary in PTX Series routers—clock signal as the system clock that is used to generate Synchronous Ethernet signal to transmit on all its interfaces.

  • The ESMC transmit module in clksyncd is notified of the quality level corresponding to the best—primary—clock. This quality level is used for ESMC packets that are transmitted out of the router.

  • ESMC packets are transmitted on all the source interfaces and on those interfaces that are configured as esmc-transmit interfaces.

The centralized mode is applicable to mobile backhaul infrastructures and for network transition from traditional TDM to Ethernet network elements with the support of Synchronous Ethernet.

Clock Selection

Configuring external clock synchronization requires making clock selection, quality level, and priority considerations. The clock selection algorithm is used to pick the two best clock sources—primary and secondary—from among the various sources.

The clock selection algorithm is on the basis of the system configuration and execution criteria such as quality level, priority, hardware restrictions, and so on, and is achieved using the following logic and restrictions:

  • The following parameters must be configured irrespective of whether the quality level is enabled or not (You can set the quality level with the set chassis synchronization source interfaces external quality-level quality-level configuration command at the [edit] hierarchy level.):

    • Quality level must be configured for nonexternal clocks.

    • In the case of option-1, the quality level must be configured for the external clocks.

    • In the case of option-2, the default quality level for the external clocks is QL_STU.

    The synchronous Ethernet Equipment Clock (EEC) synchronization networking types option-1 and option-2 map to G.813 option 1 (EEC1) and G.812 type IV clock (EEC1) standards, respectively, and can be configured at the [edit chassis synchronization] hierarchy level.

  • When the quality-mode-enable statement is included at the [edit chassis synchronization] hierarchy level, the received quality level must be equal to or better than the configured quality level for that particular source, otherwise that source is not considered for clock selection. This is so that a downstream client is guaranteed clock quality of a certain level. (Note that the term certain level here denotes the configured quality level.)

  • Configuring the quality level for a Synchronous Ethernet interface is optional when the quality-mode-enable and the selection-mode received-quality statements are included at the [edit chassis synchronization] hierarchy level.

    The default quality level value for a Synchronous Ethernet interface is:

    • SEC for the option-1 network type.

    • ST3 for the option-2 network type.

  • Configuring the priority statement is optional. When not specified, the external-a interface has a higher default priority than the external-b interface, and the external-b interface has a higher default priority than Ethernet-based sources such as ge or xe clock sources, which have the lowest default priority.

    Note:

    Configured priority is higher than any default priority.

  • During clock selection:

    • The active source with the highest quality level is selected.

    • The configured (or default) quality level of the selected clock source is used for Ethernet Synchronization Message Channel (ESMC). In order to receive or transmit ESMC messages out of an interface, at least one logical interface must be configured on that interface.

    • Table 1 explains a few scenarios that must be taken into consideration during clock selection:

      Table 1: Clock Selection Scenarios

      If

      Then

      Two or more sources have the same quality level.

      The source with highest priority is selected.

      Two or more sources have the same quality level and priority.

      The current active source, if any, among these sources is selected.

      Two or more sources have the same quality level and priority, and none of these is currently active.

      Any one of these sources is selected.

      Primary clock source is ge|xe-x/y/z, where y is even (0 or 2).

      The secondary clock source cannot be ge|xe-x/y/* or ge|xe-x/y + 1/*.

      For example, if ge-1/2/3 is the primary clock source, then the secondary clock source cannot be ge-1/2/* or ge-1/3/* for an MX80, MX240, MX480, or an MX960 router.

      Primary clock source is ge|xe-x/y/z, where y is odd (1 or 3).

      The secondary clock source cannot be ge|xe-x/y/* or ge|xe-x/y - 1/*.

      For example, if xe-2/3/4 is the primary clock source, then the secondary clock source cannot be xe-2/2/* or xe-2/3/* for an MX80, MX240, MX480, or an MX960 router.

      Primary clock source is ge|xe-x/y/z.

      The secondary clock source cannot be ge|xe-x/y/* in the case of 12-port or 16-port 10-Gigabit Ethernet DPC on an MX Series router.

      For example, if ge-0/1/2 is the primary clock source, then ge-0/1/* cannot be the secondary clock source, but ge-0/0/* can be the secondary clock source.

On PTX Series routers, you can specify the primary and secondary clock sources provided the clock source meets the necessary qualification as set by the clock algorithm. However, in the absence of any user-selected clock source, the clock source with the best quality level is selected by the clock algorithm in the router. Note that the user selection is honored even when better quality level clock sources are available. You can select the clock source with the request chassis synchronization switch clock-source operational mode command. For more information, see request chassis synchronization switch.

The clock sources used as primary or secondary clock sources cannot originate from the same FPC.

Network Option

The clock type or network option is the synchronous Ethernet Equipment Clock (EEC) synchronization networking type. You can set the network option to one of the following values:

  • option-1—This option maps to G.813 option 1 (EEC1).

  • option-2—This option maps to G.812 type IV clock (EEC1).

Note:

On MX104 routers, to configure the OC-192, OC-3, OC-12, or OC-48 interfaces as clock sources, ensure that the option-2 network option is configured.

Note:

For SCB, this option is configured with the set chassis synchronization network-type (option-1 | option-2) configuration command at the [edit] hierarchy level.

To configure the clock type, execute the set chassis synchronization network-option (option-1 | option-2) configuration command at the [edit] hierarchy level.

Note:

For Junos OS Releases 11.2R4 through 13.3R3 for MX240, MX480, MX960, MX2010, and MX2020 with SCB, SCBE or SCBE2, you must execute some specific commands after you change the network option at the [edit chassis synchronization] hierarchy level. This is because the loop bandwidth does not change automatically when you change the network option. These are the required commands:

Clock Mode

You can set the Synchronous Ethernet clock source to one of the following modes:

  • free-run—In this mode, the free-running local oscillator is used as a clock source.

    Note:

    For MX80 routers, the free-run clock is provided by the local oscillator.

    For MX240, MX480, and MX960 routers with an SCB, the free-run clock is provided by the MPCs.

    For MX240, MX480, and MX960 routers with an SCBE or an SCBE2, the free-run clock is provided by the local oscillator.

  • auto-select—In this mode, the best external clock source is selected.

By default, the auto-select option is selected.

To configure the clock mode, execute the set chassis synchronization clock-mode (free-run | auto-select) configuration command at the [edit] hierarchy level.

Quality Mode

When the quality-mode-enable statement is included at the [edit chassis synchronization] hierarchy level, the system ascertains that the clock selection algorithm uses both quality and priority of the clock sources to select the best clock source for clock synchronization. When the quality-mode-enable statement is not included, only the priority of the clock source is taken into account by the algorithm.

To enable the synchronization quality mode, include the quality-mode-enable statement at the [edit chassis synchronization] hierarchy level.

The Synchronous Ethernet ESMC quality mode is disabled by default. The Synchronous Ethernet ESMC quality mode is disabled when the quality-mode-enable statement is not included.

Selection Mode

You can specify whether the clock source selection must use the configured or the received ESMC or SSM quality level for a qualifying interface. In both selection modes, the interface qualifies for clock source selection only when the received ESMC or SSM quality level on the interface is equal to or greater than the configured ESMC or SSM quality level for the interface.

The selection modes are:

  • configured-quality—In this mode, the clock source selection algorithm uses the ESMC or SSM quality level configured for a qualifying interface.

  • received-quality—In this mode, the clock source selection algorithm uses the ESMC or SSM quality level received on the qualifying interface.

To configure the clock source algorithm selection mode, execute the set chassis synchronization selection-mode (configured-quality|received-quality) configuration command at the [edit] hierarchy level.

Note:

For the selection-mode statement to take effect, you must include the quality-mode-enable statement at the [edit chassis synchronization] hierarchy level.

Hold Interval

You can set the chassis synchronization wait time after a change in configuration, the clock selection wait time after reboot of the router, and the switchover wait time after a switchover of SCB before selecting the new clock source. The hold interval options are:

  • configuration-change—In this mode, the wait time for clock selection after a change in configuration (clock synchronization configuration) can be set from 15 seconds through 60 seconds.

  • restart—In this mode, the wait time for clock selection after reboot of the router can be set from 60 seconds through 180 seconds.

  • switchover—In this mode, the switchover wait time after clock recovery can be set from 30 seconds through 60 seconds.

To set the hold interval, execute the set chassis synchronization hold-interval (configuration-change | restart | switchover) seconds configuration command at the [edit] hierarchy level.

The default switchover wait time is 30 seconds and the default restart wait time is 120 seconds.

Switchover Mode

You can set the switchover mode to switch the clock from a lower quality source to higher quality source or to use the current clock source only. You can configure the switchover mode to one of the following:

  • non-revertive—In this mode, the router uses the current clock source as long as it is valid.

  • revertive—In this mode, the router automatically switches from a lower to a higher quality clock source whenever the higher clock source becomes available.

The default mode is revertive mode.

To configure the switching mode, execute the set chassis synchronization switchover-mode (revertive | non-revertive) configuration command at the [edit] hierarchy level.

Clock Source

You can specify the parameters that must be considered by the clock selection algorithm while selecting the best clock source. The parameters include the quality level value, the priority of the clock source, the request criteria, and the wait time to restore the interface signal to up state. You must specify these parameters on the external clock interfaces or other qualifying interfaces—which are connected to valid clock sources—to select the best clock source on the basis of the timing messages that are received on these interfaces.

For an SCBE, you can configure only one external interface and configure multiple Ethernet interfaces as needed.

On SCBE2, you can configure two external interfaces—external-0/0 and external-1/0—and configure multiple Ethernet interfaces as needed.

To configure the clock source, execute the set chassis synchronization source interfaces interface-name configuration command. You can also configure the clock source with the set chassis synchronization source interfaces external at the [edit] hierarchy level, where the external option refers to an external clock interface.

Note:

Incorporate the external option as needed on the basis of the SCB in your MX Series router.

To specify the clock source for an interface, you must set the following options:

  • priority—You can set the user priority for the selected clock source from 1 through 5.

    To set the synchronization source priority for the selected clock source, execute the set chassis synchronization source interfaces interface-name priority number configuration command or the set chassis synchronization source interfaces external priority number configuration command at the [edit] hierarchy level.

  • request—You can set the clock selection request criterion as one of the following:

    • force-switch—With this option, you can force the SCB to switch to a clock source you prefer on a particular interface (that is you can select a clock source on an interface overriding the algorithm), provided the source is enabled and not locked out. Only one configured source can be force-switched.

    • lockout—With this option configured, the clock source is not to be considered by the selection process. Lockout can be configured for any source.

    To configure these options, execute the set chassis synchronization source interfaces interface-name request (force-switch|lockout) configuration command or the set chassis synchronization source interfaces external request (force-switch|lockout) configuration command at the [edit] hierarchy level.

  • wait-to-restore—You can set the wait-to-restore time for each interface. When an interface’s signal transitions out of the signal fail state, it must be fault-free for the wait-to-restore time before it is again considered by the clock selection process. You can configure the interface signal upstate time—wait time before opening the interface to receive ESMC messages—from 0 through 12 minutes. The default time is 5 minutes. When the ESMC clock’s EEC quality level (QL) mode is enabled, it sends a signal failure to the clock selection process during the wait-to-restore time. After the wait-to-restore time ends, a new quality level value is sent to the clock selection process.

    To configure the wait-to-restore time, execute the set chassis synchronization source interfaces interface-name wait-to-restore minutes configuration command or the set chassis synchronization source interfaces external wait-to-restore minutes configuration command at the [edit] hierarchy level.

  • hold-off-time—You can configure hold-off time for Synchronous Ethernet interfaces and external clock source interfaces to prevent rapid successive switching between signal fail states. If an interface goes down, hold-off time delays short signal failures from being sent to the clock selection process.

    Note:

    During the hold-off time period, if the clock synchronization process restarts, hold-off time is not considered.

    If you configure hold-off time when the ESMC clock’s EEC QL mode is enabled, the configured quality level is used in the clock selection process during the hold-off time period. During the hold-off time period, the external clock source appears in a locked state until the hold-off time period ends. After the hold-off time period ends, a signal failure is sent to the clock selection process.

    You can configure hold-off time for a range of 300 through 1800 milliseconds. The default hold-off time is 1000 milliseconds.

    To configure hold-off time, execute the set chassis synchronization source interfaces interface-name hold-off-time configuration command at the [edit] hierarchy level.

    Note:

    When a link goes down and comes back up within the configured hold-off time in a clocking hybrid mode configuration (the combined operation of Synchronous Ethernet and Precision Time Protocol) that includes the protocols ptp slave convert-clock-class-to-quality-level configuration statement at the [edit] hierarchy level, the phase might not get locked before the timer expires. This might result in a degradation of clock quality level.

  • quality—You can set the ESMC clock’s EEC quality level as prc, prs, sec, smc, ssu-a, ssu-b, st2, st3, st3e, st4, stu, or tnc. Both option I and option II SSM quality levels are supported. Table 2 explains the quality level values.

    Table 2: Quality Levels

    Quality Level

    Description

    prc

    Timing quality of a primary reference clock (option-1 only).

    prs

    Clock traceable to a primary reference source (option-2 only).

    sec

    Timing quality of an SDH equipment clock (option-1 only).

    smc

    Clock traceable to a self-timed SONET clock (option-2 only).

    ssu-a

    Timing quality of a type I or IV client clock (option-1 only).

    ssu-b

    Timing quality of a type VI client clock (option-1 only).

    st2

    Clock traceable to Stratum 2 (option-2 only).

    st3

    Clock traceable to Stratum 3 (option-2 only).

    st3e

    Clock traceable to Stratum 3E (option-2 only).

    st4

    Clock traceable to Stratum 4 free-run (option-2 only).

    stu

    Clock traceable to an unknown quality (option-2 only).

    tnc

    Clock traceable to a transit node clock (option-2 only).

    Note:

    When the quality level is not configured and no ESMC messages are received by the clock source, then the quality level is set to DNU for option-1 and DUS for option-2. You can configure the network options, option-1 and option-2 at the [edit chassis synchronization network-option] hierarchy level.

    To avoid source looping on the selected active source—primary or secondary source, whichever is active—even when ESMC transmit is not enabled, a DNU ESMC message is sent out when the network-option statement is configured as option-1, and a DUS ESMC message is sent out when the network-option statement is configured as option-2. This is applicable only for clock sources configured on the Ethernet interfaces.

    To configure the quality level, execute the set chassis synchronization source interfaces interface-name) quality-level (prc | prs |sec | smc | ssu-a | ssu-b | st2 | st3 | st3e | st4 | stu | tnc) configuration command or the set chassis synchronization source interfaces external quality-level (prc | prs |sec | smc | ssu-a | ssu-b | st2 | st3 | st3e | st4 | stu | tnc) configuration command at the [edit] hierarchy level.

ESMC Packet Transmit

You can enable all the interfaces or configure one or more qualifying interfaces on which to permit ESMC transmit messages by executing the set chassis synchronization esmc-transmit interfaces (all |interface-name) configuration command at the [edit] hierarchy level.

Global Wait To Restore

You can globally configure the time in minutes for source ports to be up before opening the Ethernet Synchronization Message Channel (ESMC) for messages. When a port’s signal transitions out of the signal fail state, it must be fault-free for the global wait-to-restore time before it is again considered by the clock selection process.

To configure the global wait-to-restore time, include the global-wait-to-restore statement at the [edit chassis synchronization] hierarchy level.

To override the global wait-to-restore time on a specific interface, include the wait-to-restore statement at the [edit chassis source interfaces (external-a | external-b | interface interface-name)] hierarchy level.

Maximum Transmit Quality Level

To configure the maximum transmit quality level for SCBE2 as prc, prs, sec, smc, ssu-a, ssu-b, st2, st3, st3e, st4, stu, or tnc, execute the set chassis synchronization max-transmit-quality-level quality-level configuration command at the [edit] hierarchy level.

You can configure the max-transmit-quality-level statement on SCB and SCBE.

For GPS external output, when you configure the maximum transmit quality level as PRC and router is rebooted, no valid output is obtained from SCBE. However, when the maximum transmit quality level is configured to any other quality level other than PRC and the router gets rebooted, then the SCBE works normally.

Interfaces with Upstream Clock Source

You can configure the external interface to operate with a connected router for a clock source. This external interface can be configured for a clock source, which then becomes a candidate for selection as the chassis clock source by the clock source selection algorithm. You can configure several options for the external clock source interface on the SCBE and for the two external clock source interfaces on the SCBE2.

The options include E1 interface options, pulse-per-second option, the signal type for the provided reference clocks, and the T1 interface options at the [edit chassis synchronization interfaces external] hierarchy level.

The following sections explain the clock source interface parameters in detail:

E1 Interface Options

You can set the E1 interface-specific options as:

  • framing—Set the framing mode for the E1 interface as one of the following:

    • g704—G.704 framing format for E1 interfaces

    • g704-no-crc4—G.704 framing without CRC4 for E1 interfaces.

    To set the framing mode for the E1 interface, execute the set chassis synchronization interfaces external e1-options framing (g704|g704-no-crc4) configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization interfaces (external-0/0 | external-1/0) e1-options framing (g704|g704-no-crc4) configuration command at the [edit] hierarchy level for SCBE2.

    By default, the g704 framing format is selected.

  • line-encoding—Set the line-encoding statement as automatic mark inversion or high-density bipolar 3 code. The line encoding technique converts signals to bipolar pulses. You can set the line-encoding option as one of the following:

    • ami—Automatic mark inversion

    • hdb3—High-density bipolar 3 code

    To configure the line-encoding statement on the E1 interface, execute the set chassis synchronization interfaces external e1-options line-encoding (ami|hdb3) configuration command for SCBE at the [edit] hierarchy level or the set chassis synchronization interfaces (external-0/0 | external-1/0) e1-options line-encoding (ami|hdb3) configuration command at the [edit] hierarchy level for SCBE2.

    By default, the hdb3 line encoding technique is selected.

  • sabit—Set the SA bit to a value from 4 through 8. SA bits are used for exchanging the SSM quality between the clock source and the router on the E1 interface.

    To set the SA bit on the E1 interface, execute the set chassis synchronization interfaces external e1-options sabit sabit-value configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization interfaces (external-0/0 | external-1/0) e1-options sabit sabit-value configuration command at the [edit] hierarchy level for SCBE2.

Pulse Per Second

You can enable the pulse-per-second-enable option on the GPS interface to receive the pulse per second (PPS) signal by executing the set chassis synchronization interfaces external pulse-per-second-enable configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization interfaces (external-0/0 | external-1/0) pulse-per-second-enable configuration command at the [edit] hierarchy level for SCBE2.

Signal Type

You can set the frequency for the provided reference clock (GPS or BITS) as one of the following:

  • 1mhz—Set the signal with a clock frequency of 1 MHz.

  • 5mhz—Set the signal with a clock frequency of 5 MHz.

  • 10mhz—Set the signal with a clock frequency of 10 MHz.

  • 2048khz—Set the signal with a clock frequency of 2048 kHz.

  • e1—Set the signal as an E1-coded 2048 kHz signal on a 120-ohm balanced line.

  • t1—Set the signal as a T1-coded 1.544 MHz signal on a 100-ohm balanced line.

Configure the signal type by executing the set chassis synchronization interfaces external signal-type (1mhz | 5mhz | 10mhz | 2048khz | e1 | t1) configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization interfaces (external-0/0 | external-1/0) signal-type (1hz | 5mhz | 10mhz | 2048khz | e1 | t1) configuration command at the [edit] hierarchy level for SCBE2.

The 1mhz, 5mhz, and the 10mhz signals are traceable to a GPS-capable clock source, where the source can be an atomic clock. The e1 and t1 signals are traceable to a BITS clock source.

T1 Interface Options

You can set the T1 interface-specific options as:

  • framing—Set the framing mode for the T1 interface as one of the following:

    • esf—Extended superframe

    • sf—Superframe

    To set the framing mode for the T1 interface, execute the set chassis synchronization interfaces external t1-options framing (esf|sf) configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization interfaces (external-0/0 | external-1/0) t1-options framing (esf|sf) configuration command at the [edit] hierarchy level for SCBE2.

    By default, the esf framing mode is selected.

  • line-encoding—Set the line-encoding option on the T1 interface as one of the following:

    1. ami—Automatic mark inversion

    2. b8zs—8-bit zero suppression

    To configure the line-encoding option on the T1 interface, execute the set chassis synchronization interfaces external t1-options line-encoding (ami|b8zs) configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization interfaces (external-0/0 | external-1/0) t1-options line-encoding (ami|b8zs) configuration command at the [edit] hierarchy level for SCBE2.

    By default, the b8z3 line encoding technique is selected.

External Output Interface

You can set several options for the external clock output interface for SCBE or for the two external clock output interfaces for SCBE2.

The options include disabling the holdover mode; configuring a minimum quality threshold; configuring a mode to select a clock source; configuring the transmit quality level to DNU or DUS; and disabling wander filtering at the [edit chassis synchronization output interfaces external] hierarchy level for SCBE or at the [edit chassis synchronization output interfaces (external0-0 | external-1/0)] hierarchy level for SCBE2.

The following sections explain the external output interface parameters in detail:

Holdover Mode

You can disable the holdover mode on the external output interface by executing the set chassis synchronization output interfaces external holdover-mode-disable configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization output interfaces (external-0/0 | external-1/0) holdover-mode-disable configuration command at the [edit] hierarchy level for SCBE2.

Minimum Quality

When the quality of the source signal—used to derive the output—falls below a minimum quality level, the output of the external interface is placed in holdover mode. When the signal type supports the SSM quality level, the SSM quality level is set as the holdover quality level. The output interface remains in holdover mode until a source with the minimum quality level or higher is available. Note that when the holdover-mode-disable option is configured, the output is suppressed completely.

You can set the minimum quality on the external output interface as prc, prs, sec, smc, ssu-a, ssu-b, st2, st3, st3e, st4, stu, or tnc by executing the set chassis synchronization output interfaces external minimum-quality quality-level configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization output interfaces (external-0/0 | external-1/0) minimum-quality quality-level configuration command at the [edit] hierarchy level for SCBE2.

Source Mode

When the source mode is set to chassis, the source selected by the chassis clock module is used as the clock source. When the source mode is set to line, the best available line clock is selected.

You can set the source mode for selecting a clock source as either a chassis clock or the best line clock source as output by executing the set chassis synchronization output interfaces external source-mode (chassis|line) configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization output interfaces (external-0/0 | external-1/0) source-mode (chassis|line) configuration command at the [edit] hierarchy level for SCBE2.

Transmit Quality Level

You can configure the tx-dnu-to-line-source-enable statement to enable the transmit quality level to DNU or DUS when the chassis clock is the BITS input signal and when a valid line source signal is sent out through the BITS output.

You can set the transmitting quality level to DNU or DUS on the line source interface by executing the set chassis synchronization output interfaces external tx-dnu-to-line-source-enable configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization output interfaces (external-0/0 | external-1/0) tx-dnu-to-line-source-enable configuration command at the [edit] hierarchy level at SCBE2.

Wander Filter

You can disable the wander filter by executing the set chassis synchronization output interfaces external wander-filter-disable configuration command at the [edit] hierarchy level for SCBE or the set chassis synchronization output interfaces (external-0/0 | external-1/0) wander-filter-disable configuration command at the [edit] hierarchy level for SCBE2.

Clock Synchronization Ports

You can set the time-of-day-format statement as an ASCII string on SCBE and SCBE2 by executing the set chassis synchronization port auxiliary client time-of-day-format ascii string configuration command at the [edit] hierarchy level.

The time of day (TOD) format is specified as a string of ASCII characters. The TOD format string contains information that specifies which ASCII characters to match, which ASCII characters to ignore, and which ASCII characters to translate to particular time units (such as month, day, hour, minute, and so on).

The TOD format string specifies how the incoming string is to be parsed so that the information embedded can be extracted. The format of the TOD option can be executed with the set chassis synchronization port auxiliary time-of-day-format ascii string configuration command at the [edit] hierarchy level, where the format of the data string is $GPRMC,%hh%mm%ss,^,^^^^.^^,^,^^^^^^^^,^,^^^^^,^^^^^,%DD%MM%YY,^^^^^,^*^^.

Table 3 explains pattern-matching characters used in the TOD data string.

Table 3: Pattern-Matching Characters

Character construct

Number of characters

Description

-

1

The DO NOT CARE (DNC) character

%hh

2

Hours (00–23)

%mm

2

Minutes (00–59)

%ss

2

Seconds (00–59)

%DD

2

Day (01–31)

%MM

2

Month (01–12)

%YY

2

Year without century

%YYY

4

Year with century

%DDD

3

Day of year (001–366)

%MMM

3

Month of year (JAN, FEB, etc.)

%cc

2

NMEA message checksum

%Q

1

Time quality indicator (‘ ‘ = valid ‘*’ = error)

There are several patterns that can be received by a router. The following pattern shows an example of a received TOD data string (as defined in the National Marine Electronics Association (NMEA) 0183 standard. The data string is called the Recommended Minimum Specific GPS/Transit Data (RMC) message.) and Table 4 explains it in detail.

Table 4: Received TOD Data String

Pattern

Description

$GPRMC

NMEA sentence ID

225446

UTC time of fix (22:54:46 UTC)

A

Data status (A=Valid position, V=navigation receiver warning)

4916.45

Latitude of fix

N

N or S of longitude

12311.12

Longitude of fix

W

E or W of longitude

000.5

Speed over ground in knots

054.7

Track made good in degrees True

191194

UTC date of fix (19 November 1994)

020.3

Magnetic variation degrees

E

E or W of magnetic variation

*68

Checksum (XOR of all characters between $ and *)

Note:

Whenever a TOD data string does not provide sufficient information, the router extracts it from Junos OS and generates a log message. The TOD data string that is either transmitted or received is always of fixed length and is delimited by a <CR><LF>character pair, where CR (carriage return) and LF (line feed) are the line break types used to end the ASCII format string.

MIC-Level Framing Mode

You can configure the LAN framing mode on the 10-Gigabit Ethernet MIC with XFP by executing the set chassis fpc fpc-slot pic pic-slot framing lan at the [edit] hierarchy level.

Note that to operate in LAN framing mode on the 10-Gigabit Ethernet MIC with XFP, you must configure the interface framing mode on the MIC interface. Execute the set interfaces xe-fpc/pic/port framing-mode (lan-phy | wan-phy) configuration command at the [edit] hierarchy level, where the lan-phy option denotes a 802.3ae 10-Gbps LAN-mode interface and the wan-phy option denotes a 802.3ae 10-Gbps WAN-mode interface.

Automatic Clock Selection

Automatic clock selection is the selection of the best quality clock source by the clock source selection algorithm based on the Ethernet Synchronization Message Channel (ESMC) Synchronization Status Message (SSM) quality level, the configured quality level, and the priority.

Clock Source Selection Algorithm

The clock source selection algorithm uses the following logic and restrictions:

  • QL must be configured for non-external clocks, whether or not QL is enabled.

  • For network-option option-1, QL must be configured for external clocks (gps or bits) whether or not QL is enabled.

  • In the case of network-option option-2, the default QL for the external clocks is QL_STU, whether or not QL is enabled.

  • Configuring priority is optional. When not specified, gps has a higher default priority than bits, and bits has a higher default priority than Gigabit Ethernet, 10-Gigabit Ethernet, and T1 or E1 clock, which have the lowest default priority.

  • When QL is enabled, the received QL must be equal to or better than the configured QL for that particular source or else that source will not be considered for clock selection. This is so that a downstream client is guaranteed clock quality of a certain level (that “certain level” being the configured QL).

During clock selection:

  • The active source with the highest QL is selected.

  • If QL is the same for two or more sources, then the source with the highest priority is selected.

  • If two or more sources have the same QL and priority, then the currently active source, if any, among these sources is selected.

  • If two or more sources have the same QL and priority, and none of these is currently active, then any one of these may be selected.

  • If selection-mode is configured quality, then the configured (or default) QL of the selected clock source is used for transmitting ESMC. If selection-mode is received quality, then the received QL of the selected clock source is used for ESMC transmit.

  • In order to receive or transmit ESMC messages out of an interface, at least one logical interface should be configured on that interface. If the interface is currently not configured with a logical interface, you may do so using the set interfaces interface-name unit 0 statement at the edit hierarchy level.

The clock source selection algorithm is triggered by the following events:

  • Changes in the received ESMC SSM quality level (QL)

  • Configuration changes. For example, the addition or deletion of a clock source, a change to the QL mode, and so on.

  • Signal failure detected on the currently selected source.

When the router is configured with automatic clock selection, the system chooses up to two best upstream clock sources. The system then uses the clock recovered from one of the sources to lock the chassis clock. If an upstream clock with acceptable good quality is not available or if the system is configured in free-run mode, the system uses the internal oscillator.

Clock Selection and Quality Level

Automatic clock selection supports two modes: QL enabled and QL disabled.

  • QL disabled— In this mode, the best clock is selected based on the configured ESMC SSM QL. If the QL of the configured clocks are equal, the clock selection is based on the configured priority. If both the configured QL and priority are equal, one of the sources is randomly selected. Absence of the quality-mode-enable statement at the [edit chassis synchronization] hierarchy level means that QL is disabled.

    Note:

    The default setting is QL disable.

  • QL enabled—In this mode, the best clock is selected based on the incoming ESMC SSM QL as long as the incoming QL is at least as good as the source’s configured QL. If the QLs are equal, the clock selection is based on the configured priority. If both the received QL and the priority are equal, one of the sources is selected randomly.

Selection Mode for the Incoming ESMC Quality

Depending on the configuration, the clock source selection algorithm uses the configured or received ESMC SSM quality level for clock selection. In both configured and received selection modes, the interface qualifies for clock source selection only when the received ESMC SSM quality level on the interface is equal to or greater than the configured ESMC SSM quality level for the interface.

Automatic Clock Selection for ACX Series Routers

The ACX Series Universal Metro routers support external clock synchronization and automatic clock selection for Synchronous Ethernet, T1 or E1 line timing sources, and external inputs. Configuring external clock synchronization and automatic clock selection requires making clock selection, quality level (QL), and priority considerations. The clock source selection algorithm is used to pick the two best upstream clock sources from among all the various sources, based on system configuration and execution criteria such as QL, priority, and hardware restrictions.

With automatic clock selection, the system chooses up to two best upstream clock sources. The system then uses the clock recovered from one of the sources to lock the chassis clock. If an upstream clock with acceptable good quality is not available or if the system is configured in free-run mode, the system uses the internal oscillator. The following automatic clock selection features are supported for Synchronous Ethernet, T1 or E1 line timing sources, and external inputs:

Note:

Automatic clock selection does not apply to the IEEE 1588v2 recovered clock.

Automatic clock selection is supported on the ACX Series routers. Automatic clock selection of the best quality clock source is based on the Ethernet Synchronization Message Channel (ESMC) Synchronization Status Message (SSM) quality level, the configured quality level, and the priority. To configure automatic clock selection, include the auto-select option at the [edit chassis synchronization] hierarchy level. You can also configure the chassis to lock to the free-running local oscillator, which is the Stratum 3E oscillator, by including the free-run option at the [edit chassis synchronization] hierarchy level. The auto-select option enables the clock source selection algorithm to run. The clock source selection algorithm is triggered by the following events:

  • Signal failure detected on the currently selected source

  • Changes in the received Ethernet Synchronization Message Channel (ESMC) Synchronization Status Message (SSM) quality level (QL)

  • Configuration changes. For example, the addition or deletion of a clock source, a change to the QL mode, and so on.

Automatic clock selection supports two modes on the ACX Series router: QL enabled and QL disabled. To configure QL mode, include the quality-mode-enable statement at the [edit chassis synchronization] hierarchy level.

  • QL disabled—The default setting is disable, which means that when the quality-mode-enable statement is not configured, QL is disabled. In this mode, the best clock is selected based on the configured ESMC SSM QL. If the QL of the best clocks are equal, the clock selection is based on the configured priority. If both the configured QL and priority are equal, one of the sources is randomly selected.

  • QL enabled—In this mode, the best clock is selected based on the incoming ESMC SSM QL as long as the incoming QL is at least as good as the source’s configured QL. If the QLs are equal, the clock selection is based on the configured priority. If both the received QL and the priority are equal, one of the sources is selected randomly.

Interface and Router Clock Sources

Interface and Router Clock Sources Overview

When configuring the router, you can configure the transmit clock on each interface; the transmit clock aligns each outgoing packet transmitted over the router’s interfaces. For both the router and interfaces, the clock source can be the router’s internal Stratum 3 clock, which resides on the control board, or an external clock that is received from the interface you are configuring. For example, interface A can transmit on interface A’s received clock (external, loop timing) or the Stratum 3 clock (internal, line timing). Interface A cannot use a clock from any other source.

By default, each interface uses the router’s internal Stratum 3 clock. To configure the clock source of each interface, include the clocking statement at the [edit interfaces interface-name] hierarchy level:

System reference clocks can be generated from different system components, depending on the router type. For example, Figure 1 illustrates the different clock sources on the M120 router.

Figure 1: M120 Router Clock Sources M120 Router Clock Sources

Configure an External Clock Synchronization Interface

The M40e, M120, M320, T640, and T1600 routers support an external synchronization interface that can be configured to synchronize the internal Stratum 3 clock to an external source, and then synchronize the chassis interface clock to the external source.

This feature can be configured for external primary and secondary interfaces that use Building Integrated Timing System (BITS) or SDH Equipment Timing Source (SETS) timing sources, or an equivalent quality timing source. When internal timing is set for SONET/SDH, Plesiochronous Digital Hierarchy (PDH), and digital hierarchy (DS1) interfaces on the Physical Interface Cards (PICs), the transmit clock of the interface is synchronized to BITS/SETS timing and traceable to timing within the network.

Routers and switches that support an external clock synchronization interface include:

  • M40e, M120, and M320 routers

  • T640 and T1600 routers

To configure external synchronization on the router, include the synchronization statement at the [edit chassis] hierarchy level:

Use the synchronization statement options to specify a primary and secondary timing source. To do this, configure the following options:

  • For the M120 and M320 routers, specify a signal type mode for interfaces, either t1 or e1. For the M40e, T640, and T1600 routers, only the t1 signal type mode is supported. The default setting is t1.

  • For the T640 and T1600 routers, external clock interfaces are supported on the SONET Clock Generators (SCG-T-EC). The external clock interfaces on the SONET Clock Generators (SCG-T) are not supported.

  • Specify the switching mode as revertive if a lower-priority synchronization can be switched to a valid, higher-priority synchronization.

  • For the M320 router, specify that a single signal should be wired to both Control Boards (CBs) using a Y-cable. For the M40e router, the signal is wired to the CIP and Y-cable functionality is embedded in this system.

    The y-cable-line-termination option is not available on the M40e, M120, T640, and T1600 routers.

  • Control whether the diagnostic timing signal is transmitted.

    The transmitter-enable option is not available on the M120, T640, and T1600 routers.

  • Set a validation interval. The validation-interval option validates the synchronized deviation of the synchronization source. If revertive switching is enabled and a higher-priority clock is validated, the clock module is directed to the higher-priority clock, and all configured and active synchronizations are validated. The validation timer resumes after the current validation interval expires. The validation interval can be a value from 90 through 86,400 seconds. The default value is 90 seconds. For the M120 router, the range for the validation-interval option is 30 through 86,400 and the default value is 30.

  • Specify the primary external timing source by using the primary (external-a | external-b) statement.

  • Specify the secondary external timing source by using the secondary (external-a | external-b) statement.

Configure External Clock Synchronization for ACX Series Routers

The ACX Series Routers support external clock synchronization for Synchronous Ethernet, T1 or E1 line timing sources, and external inputs. Configuring external clock synchronization requires making clock selection, quality level (QL), and priority considerations. The clock source selection algorithm is used to pick the two best upstream clock sources from among all the various sources, based on system configuration and execution criteria such as QL, priority, and hardware restrictions.

To configure external synchronization on the router, include the synchronization (ACX Series) statement at the [edit chassis] hierarchy level.

Setting the Ethernet equipment clock (EEC) network type

The network type options set the frequency of the configured clock. When bits is configured with option-1 on the ACX router, the Synchronous Ethernet equipment is optimized for 2048 Kbps, the speed of an E1 interface. When bits is configured with option-2 on the ACX router, the Synchronous Ethernet equipment is optimized for 1544 Kbps, the speed of a T1 interface. To set the clock type, use the following command:

For option-1, QL must be configured for external clocks (gps or bits) whether or not QL is enabled. For option-2, the default QL for external clocks is QL_STU whether or not QL is enabled.

The following output shows an example of the configuration of the network type with option-1:

Setting the clock mode

Clock mode sets the selection of the clock source from a free-running local oscillator or from an external qualified clock. The default clock mode is auto-select, which uses the best clock source. To set the clock mode, use the following command:

The following output shows an example of the configuration of the free-run option:

Note:

Automatic clock selection does not apply to the IEEE 1588v2 recovered clock.

Setting the quality mode

Specify the expected quality of the incoming clock on this source. The default is disable. To set the synchronization quality mode, use the following command:

The following output shows the configuration of the quality-mode-enable statement:

Setting the selection mode

The selection mode specifies whether the clock source selection algorithm should use the configured or received ESMC SSM quality level for clock selection. In both selection modes (configured-quality and received-quality), the interface qualifies for clock source selection only when the received ESMC SSM quality level on the interface is equal to or greater than the configured ESMC SSM quality level for the interface. To configure the ESMC SSM quality-based clock source selection mode, use the following command:

The following output shows the configuration of the selection-mode statement with the configured-quality option and the mandatory quality-mode-enable statement:

Note:

For the selection-mode statement configuration to take effect, you must set the quality-mode-enable statement at the [edit chassis synchronization] hierarchy level.

Setting the time interval before a new clock source is selected

For routers operating with Synchronous Ethernet , set the time interval to wait before the router selects a new clock source. After a change in the configuration, the time to wait is between 15 and 60 seconds. After a reboot (restart), the time to wait is from 60 to 180 seconds. After clock recovery (switchover), the time to wait is from 30 to 60 seconds. The default switchover time is 30 seconds and cold boot time is 120 seconds. To set the time interval before a new clock source is selected, use the following command:

The following output shows the configuration of the hold-interval statement with the configuration-change option:

Setting the synchronization switching mode

The configured switching mode determines the clock source used. In revertive mode, the system switches from a lower to a higher quality clock source whenever the higher clock source becomes available. In non-revertive mode, the system continues to use the current clock source as long as it is valid. The default mode is revertive. To set the synchronization switchover mode, use the following command:

The following output shows the configuration of the switchover-mode statement with the non-revertive option:

Setting the clock source

The configured clock source is the candidate for selection by the clock selection algorithm. The clock source can be the router’s BITS T1 or E1 interface, GPS, or an interface with an upstream clock source. To set the clock source, use the following command:

The following output shows the configuration of the source statement with the bits option and the mandatory network-option statement. When bits is configured with option-1 on the ACX2000 router, the Synchronous Ethernet equipment is optimized for 2048 Kbps, the speed of an E1 interface.

Note:

For the source statement configuration to take effect, you must set the network-option (option-1 | option-2) statement at the [edit chassis synchronization] hierarchy level.

The bits option is not supported on the ACX1000 router.

Setting ESMC transmit interface

The ESMC transmit interface is the interface on which ESMC transmit messages are permitted. To enable ESMC packet transmit, use the following command:

The following output shows the configuration of the esmc-transmit statement:

You can also enable ESMC on all interfaces with the interfaces all statement at the preceding hierarchy level.

Setting the synchronization source quality level

Specify the expected quality of the incoming clock on this source. Specific quality-level options are valid depending on the configured network-option; option-1 or option-2. Both option-1 and option-2 SSM quality levels are supported. To set the synchronization source quality level, use the following command:

The following output shows the configuration of the quality-level statement configured with the prc option:

Setting the synchronization source priority

Specify a priority level between 1 and 5. When not specified, gps has a higher priority than bits,and bits has a higher default priority than other Gigabit Ethernet or 10 Gigabit Ethernet clock sources, which have the lowest priority. To set the synchronization source priority, use the following command:

The following output shows the configuration of the priority statement:

Setting the synchronization source wait to restore time

A wait-to-restore time can be configured for each port. When a port’s signal transitions out of the signal fail state, it must be fault free for the wait-to-restore time before it is again considered by the selection process. The range is from 0 through 12 minutes. The default time is 5 minutes.

To set the synchronization source wait-to-restore time, use the following command:

The following output shows the configuration of the wait-to-restore statement:

Setting the synchronization source lockout

A lockout may be configured for any source. When a lockout is configured for a source, that source will not be considered by the selection process. To set the synchronization source lockout, use the following command:

The following output shows the configuration of the request lockout statement:

Setting the forced switch

Force a switch to the source provided that the source is enabled and not locked out. Only one configured source may be force-switched. To set the forced switch, use the following command:

The following output shows the configuration of the request force-switch statement:

Configure External Clock Synchronization for MX Series Routers

MX Series routers support external clock synchronization for Synchronous Ethernet, T1 or E1 line timing sources, and external inputs. Configuring external clock synchronization requires making clock selection, quality level, and priority considerations. The clock source selection algorithm is used to pick the two best upstream clock sources from among the various sources on the basis of system configuration and execution criteria such as quality level, priority, and hardware restrictions.

The following sections explain configuring clock synchronization options for MX Series routers:

Note:

The following scenarios occur when you configure Synchronous Ethernet without the clock-class-to-quality-level-mapping statement at the [edit protocols ptp slave] hierarchy level:

  • Qualified clock source quality level (that is the secondary clock source quality level) is transmitted out of the external interface and the Ethernet interface during clock reference switchover when two clock sources on different MICs of the same FPC exist or when two clock sources on two different FPCs exist.

  • Lower quality level is transmitted out the external interface and the Ethernet interface during clock reference switchover when two clock sources on the same MIC of an FPC exist due to hardware limitation.

Before you remove the SCBE from the router, you must delete the configuration under the [edit chassis synchronization] hierarchy level. Similarly, before you remove the SCBE2 from the router, you must delete the configuration under the [edit chassis synchronization] hierarchy level.

On SCBE2, the external-0/0 interface is located on SCB0 and the external-1/0 interface is located on SCB1.

Configure Clock Synchronization Options

To configure the clock synchronization options.

  1. In configuration mode, go to the [edit chassis synchronization] hierarchy level.
  2. Configure the Synchronous Ethernet clock selection mode as auto-select or free-run.
  3. Configure the ESMC transmit parameters on all the interfaces or on selected interfaces.
  4. Configure the hold interval as configuration-change, which is the wait time (from 15 seconds through 60 seconds) after a change in configuration; restart, which is the wait time (from 60 seconds through 180 seconds) after reboot of the router; and switchover, which is the switchover wait time (from 30 seconds through 60 seconds) after clock recovery.
  5. Configure the options for the external interfaces on the basis of the type of Enhanced Switch Control Board on your MX Series router.

    The SCBE has only one external interface. Configure the following options for SCBE:

    1. Go to the [edit chassis synchronization interfaces external] hierarchy level.
    2. Configure all the E1 interface-specific options—the framing statement as g704 or g704-no-crc, the line-encoding statement as ami or hdb3, and the sabit statement from 4 bits through 8 bits.
    3. Configure the pulse-per-second-enable statement to enable the pulse per second (PPS) signal to be received on the GPS interface.
    4. Configure the frequency for the provided reference clock as 1 MHz, 5 MHz, 10 MHz, 2048 kHz, e1, or t1.
    5. Configure the T1 interface-specific options—the framing statement as esf or sf and the line-encoding statement as ami or b8zs.

    The SCBE2 Control Board has two external interfaces—external-0/0 and external-1/0. Configure the following options for SCBE2 Control Board:

    1. Go to the [edit chassis synchronization interfaces external-0/0] or [edit chassis synchronization interfaces external-1/0] hierarchy level.

      OR

    2. Configure all the E1 interface-specific options—the framing statement as g704 or g704-no-crc, the line-encoding statement as ami or hdb3, and the sabit statement from 4 bits through 8 bits-—on the external-0/0 interface or the external-1/0 interface.
    3. Configure the pulse-per-second-enable statement to enable the pulse per second (PPS) signal to be received on the GPS interface of the router.
    4. Configure the frequency for the provided reference clock as 1 MHz, 5 MHz, 10 MHz, 2048 kHz, e1, or t1.
    5. Configure the T1 interface-specific options—the framing statement as esf or sf and the line-encoding statement as ami or b8zs.

    The MX2020 Control Board has two external interfaces—external-a and external-b. Configure the following options for MX2020 Control Board:

    1. Go to the [edit chassis synchronization interfaces external-a] or [edit chassis synchronization interfaces external-b] hierarchy level.

      OR

    2. For BITS interface, configure all the E1 interface-specific options—the framing statement as g704 or g704-no-crc, the line-encoding statement as ami or hdb3, and the sabit statement from 4 bits through 8 bits-—on the external-a interface or the external-b interface.
    3. Configure the pulse-per-second-enable statement to enable the pulse per second (PPS) signal to be received on the GPS interface of the router.
    4. Configure the frequency for the provided reference clock as 1 MHz, 5 MHz, or 10 MHz for GPS interface and 2048 kHz, e1, or t1 for BITS interface.
    5. For BITS interface, configure the T1 interface-specific options—the framing statement as esf or sf and the line-encoding statement as ami or b8zs.
  6. Configure the maximum transmit quality level as prc, prs, sec, ssu-a, ssu-b, st2, st3e, stu, or tnc.
  7. Configure the EEC synchronization networking type as option-1 or option-2.
  8. Configure the options for the external clock interface output on the basis of the type of Enhanced Switch Control Board on your MX Series router.

    For SCBE:

    1. Go to the [edit chassis synchronization output interfaces external] hierarchy level.
    2. Configure all the external clock interface output options. The options include the holdover-mode-disable statement; the minimum-quality statement, which can be set as prc, prs, sec, ssu-a, ssu-b, st2, st3e, stu, or tnc; the source-mode statement, which can be set as chassis or line; the tx-dnu-to-line-source-enable statement; and the wander-filter-disable statement.

    For SCBE2:

    1. Go to the [edit chassis synchronization output interfaces external-0/0] hierarchy level or the [edit chassis synchronization output interfaces external-1/0] hierarchy level.
    2. Configure all the external clock interface output options on the external-0/0 interface or the external-1/0 interface. The options include the holdover-mode-disable statement; the minimum-quality statement, which can be set as prc, prs, sec, ssu-a, ssu-b, st2, st3e, stu, or tnc; the source-mode option, which can be set as chassis or line; the tx-dnu-to-line-source-enable statement; and the wander-filter-disable statement.

    For MX2020 Control Board:

    1. Go to the [edit chassis synchronization output interfaces external-a] hierarchy level or the [edit chassis synchronization output interfaces external-b] hierarchy level.
    2. Configure all the external clock interface output options on the external-a interface or the external-b interface. The options include the holdover-mode-disable statement; the minimum-quality statement, which can be set as prc, prs, sec, ssu-a, ssu-b, st2, st3e, stu, or tnc; the source-mode option, which can be set as chassis or line; the tx-dnu-to-line-source-enable statement; and the wander-filter-disable statement.
  9. Configure the time-of-day message format as ASCII on the auxiliary port that receives the external clock signals.
  10. Configure the quality-mode-enable statement to enable Synchronous Ethernet ESMC quality mode.
  11. Configure the selection mode for the incoming ESMC quality as configured-quality or received-quality.
  12. Configure the options for the ESMC source related external clock source interface on the basis of the type of Enhanced Switch Control Board on your MX Series router.

    For SCBE:

    1. Go to the [edit chassis synchronization source interfaces external] hierarchy level or the [edit chassis synchronization source interfaces ethernet-interface-name] hierarchy level.

      OR

    2. Configure the external clock interface and the Ethernet interface with their options. Configure the priority statement from 1 through 5; the quality-level statement as prc, prs, sec, ssu-a, ssu-b, st2, st3e, stu, or tnc; the request statement as force-switch or lockout; the wait-to-restore statement from 0 minutes to 12 minutes; and the hold-off-time statement from 300 through 1800 milliseconds. You can configure the same options for the Ethernet interfaces as well.

    For SCBE2 Control Board:

    1. Go to the [edit chassis synchronization source interfaces (external-0/0] hierarchy level or the [edit chassis synchronization source interfaces (external-1/0] hierarchy level.

      OR

    2. Configure the options on the external-0/0 interface or the external-1/0 interface. Set the priority statement from 1 through 5; the quality-level statement as prc, prs, sec, ssu-a, ssu-b, st2, st3e, stu, or tnc; the request statement as force-switch or lockout; the wait-to-restore statement from 0 minutes to 12 minutes; and the hold-off-time statement from 300 through 1800 milliseconds.

    For MX2020 Control Board:

    1. Go to the [edit chassis synchronization source interfaces (external-a] hierarchy level or the [edit chassis synchronization source interfaces (external-b] hierarchy level.

      OR

    2. Configure the options on the external-a interface or the external-b interface. Set the priority statement from 1 through 5; the quality-level statement as prc, prs, sec, ssu-a, ssu-b, st2, st3e, stu, or tnc; the request statement as force-switch or lockout; the wait-to-restore statement from 0 minutes to 12 minutes; and the hold-off-time statement from 300 through 1800 milliseconds.
  13. Configure the switchover mode as revertive or non-revertive.

Display the External Clock Synchronization Configuration for SCB

Purpose

Display the options for external clock synchronization for SCB.

Action

Execute the show command at [edit chassis] hierarchy level.

Display the External Clock Synchronization Configuration for SCBE

Purpose

Display the options for external clock synchronization for SCBE. Note that the SCBE has only one external interface.

Action

Execute the show command at [edit chassis] hierarchy level.

Display the External Clock Synchronization Configuration for SCBE2

Purpose

Display the options for external clock synchronization for SCBE2. SCBE2 has two external interfaces, external-0/0 and external-1/0.

Action

Execute the show command at [edit chassis] hierarchy level.

Display the External Clock Synchronization Configuration for MX2020 Control Board

Purpose

Display the options for external clock synchronization for MX2020 Control Board. MX2020 Control Board has two external interfaces, external-a and external-b.

Action

Execute the show command at [edit chassis] hierarchy level.

Clock Sources for PTX Series Routers

System clocking on PTX Series Packet Transport Routers is controlled by a Centralized Clock Generator (CCG). The CCG is capable of deriving a primary clock from a valid source and synchronizing all interfaces on the chassis to this primary clock. The CCG plugs into the rear of the chassis. A pair of CCGs installed in the chassis provide a redundant fallback option.

Synchronous Ethernet is configured on external primary and secondary interfaces that use building-integrated timing system (BITS), SDH Equipment Timing Source (SETS) timing sources, or an equivalent quality timing source such as GPS. On the PICs, the transmit clock of the interface is synchronized to a BITS or SETS timing source and is traceable to the timing source within the network.

PTX Series Packet Transport Routers can use an internal clock source or it can extract clocking from an external source.

Clock sources and specifications include:

  • The PTX Series Packet Transport Router clock is a Stratum 3E-compliant clock with Free Run +/- 4.6 ppm/20 years, Holdover +/- 0.01 ppm/24 hours, and Drift +/- 0.001 ppm/24 hours.

  • The internal clock is based on Freerun OCXO with +/- 10 ppb accuracy.

  • External clocking includes a choice of GPS-based clock recovery (5 MHz and 10 MHz) or BITS-T1/E1 Line synchronization (1.544 MHz and 2.048 MHz).

  • Synchronous Ethernet is supported based on the ITU-T G.8261, ITU-T G.8262, and ITU-T G8264 specifications with line timing from the 10-Gigabit Ethernet, 40-Gigabit Ethernet, or 100-Gigabit Ethernet interface.

    Synchronous Ethernet is a key requirement for circuit (emulation) services and mobile radio access technologies. Synchronous Ethernet supports sourcing and transfer of frequency for synchronization purposes for both wireless and wireline services and is primarily used for mobile backhaul and converged transport.

Figure 2: Clocking Example for PTX Series Packet Transport Routers Clocking Example for PTX Series Packet Transport Routers

In this example, the interface et-7/1/1 is configured as the primary clock source and GPS1 as the secondary clock source.

Note that you can specify the primary and secondary clock sources provided that the clock source meets the necessary qualification as set by the clock algorithm. However, in the absence of any user-selected clock source, the clock source with the best quality level is selected by the clock algorithm in the router. Note that the user selection is honored even when better quality level clock sources are available. You can select the clock source with the request chassis synchronization switch clock-source operational mode command. For more information, see request chassis synchronization switch.

Note:

The clock sources used as primary or secondary clock sources cannot originate from the same FPC.

For more information about clock source ports, see PTX3000 Clocking Port Cable Specifications and Pinouts, PTX5000 Centralized Clock Generator Description, and Connecting the PTX5000 to an External Clocking Device.

Getting Started to Configure Clock Synchronization on PTX Series Routers

System clocking on PTX Series Packet Transport Routers is controlled by a Centralized Clock Generator (CCG). The CCG is capable of deriving a primary clock from a valid source and synchronizing all interfaces on the chassis to this primary clock.

Table 5: Locating the Information You Need to Configure Clock Synchronization on PTX Series Routers

Task You Need to Perform

Where The Information Is Located

Configure a clock source.

Synchronizing Internal Stratum 3 Clock to External Clock Sources on PTX Series Routers

synchronization (PTX Series)

Identify clock sources.

Clock Sources for PTX Series Packet Transport Routers

Change the clock source.

request chassis synchronization switch

Configure the clock source mode to be revertive or non-revertive.

switchover-mode

Verify the clock source is operational.

show chassis synchronization

Synchronize Internal Stratum 3 Clock to External Clock Sources on PTX Series Routers

The PTX Series Packet Transport Routers support an external synchronization interface that can be configured to synchronize the internal Stratum 3 clock to an external source, and then synchronize the chassis interface clock to that source. You can also configure a primary and a secondary clock source.

The following tasks explain how to configure a recovered clock for an FPC and to configure the clock synchronization options:

Configure a Recovered Clock for an FPC

To configure a recovered clock for an FPC on PTX Series routers:

  1. Go to the [edit chassis fpc slot-number pic pic-number] hierarchy level.
  2. Configure a port from 0 through 47 through which the clock is recovered.

Configure External Clock Synchronization Options

You must configure a recovered clock (recovered-clock port port-number) for an interface before configuring clock synchronization options for the same interface.

Use the synchronization statement options to specify a primary and a secondary timing source. To do this, you must configure the following options:

  • Specify the switching mode as revertive when a lower-priority synchronization source is to be switched to a valid, higher-priority synchronization source.

  • Specify the primary external timing source with the primary (fpc-slot-number | gps-0 | gps-1 | bits-a | bits-b) statement.

  • Specify the secondary external timing source with the secondary (fpc-slot-number | gps-0 | gps-1 |bits-a | bits-b) statement.

To configure the clock synchronization options:

  1. In configuration mode, go to the [edit chassis synchronization] hierarchy level.
  2. Configure the Synchronous Ethernet clock selection mode as auto-select to select the best external clock source or free-run to use the free-running local oscillator as a clock source.
  3. Configure the ESMC transmit parameters on all the interfaces or on selected interfaces.
  4. Configure the hold interval as configuration-change, which is the wait time (from 15 seconds through 60 seconds) after a change in configuration; restart, which is the wait time (from 60 seconds through 180 seconds) after reboot of the router; and switchover, which is the switchover wait time (from 30 seconds through 60 seconds) after clock recovery.
  5. Configure the interface with an available upstream clock source where the clock source is bits-a, bits-b, gps-0, or gps-1. Configure the pulse-per-second-enable statement to enable the pulse per second (PPS) signal to be received on the GPS interface and configure the frequency for the provided reference clock as 5 MHz, 10 MHz, e1, or t1.
  6. Configure the maximum transmit quality level as prc, prs, sec, ssu-a, ssu-b, st2, st3e, stu, or tnc.
  7. Configure the EEC synchronization networking type as option-1 to map to G.813 option 1 (EEC1)or option-2 to map to G.812 type IV clock (EEC1).
  8. Configure the primary synchronization reference source as bits-a, bits-b, gps-0, gps-1, fpc-0, fpc-1, fpc-2, fpc-3, fpc-4, fpc-5, fpc-6, or fpc-7. The selected source is considered to be the best choice among the available sources.
  9. Configure the quality-mode-enable statement to enable Synchronous Ethernet ESMC quality mode.
  10. Configure the secondary synchronization reference source as bits-a, bits-b, gps-0, gps-1, fpc-0, fpc-1, fpc-2, fpc-3, fpc-4, fpc-5, fpc-6, or fpc-7. The selected source is considered to be the best alternative among the available sources.
  11. Configure the quality selection mode for the incoming ESMC packets as configured-quality or received-quality.
  12. Configure the ESMC source as bits-a, bits-b, gps-0, or gps-1. For the configured source, configure the priority statement from 1 through 5; the quality-level statement as prc, prs, sec, ssu-a, ssu-b, st2, st3e, stu, or tnc; the request statement as force-switch or lockout.
  13. Configure the switchover mode as revertive or non-revertive.
Note:

To configure the Synchronous Ethernet clock sources, you must configure network-option option, quality-mode-enable, and source interfaces interface-name priority value quality-level level along with other parameters as needed at the [edit chassis synchronization] hierarchy level.

To configure ESMC transmit interface, you must configure esmc-transmit interface interface-name along with other parameters as needed at the [edit chassis synchronization] hierarchy level.