PTP Transparent Clocks

The Precision Time Protocol (PTP) standardized by IEEE 1588 improves the current methods of synchronization used within a distributed network. You can use PTP across packet-based networks including, but not limited to, Ethernet networks. Queuing and buffering delays in the switch can cause variable delay to packets, which affects path delay measurements. Queuing delays vary based on the network load and also depend on the architecture of the switch or the router.

Transparent clocks measure and adjust for packet delay. The transparent clock computes the variable delay as the PTP packets pass through the switch or the router.

Transparent clocks improve synchronization between the timeTransmitter and timeReceiver clocks and ensure that the timeTransmitter and timeReceiver clocks are not impacted by the effects of packet delay variation. The transparent clock measures the residence time (the time that the packet spends passing through the switch or the router), and adds the residence time into the correction field of the PTP packet. The timeReceiver clock accounts for the packet delay by using both the timestamp of when it started and the information in the correction field.

With an end-to-end transparent clock, only the residence time is included in the correction field of the PTP packets. The residence timestamps are sent in one packet as a one-step process. In a two-step process, estimated timestamps are sent in one packet, and additional packets contain updated timestamps.

You can enable or disable a transparent clock globally for the switch or router. With a global configuration, the same configuration is applied to each interface. If the transparent clock is disabled, PTP packet correction fields are not updated. If the transparent clock is enabled, the PTP packet correction fields are updated.

You can configure the syntonized-end-to-end (E2E) transparent clock for Precision Time Protocol (PTP). In syntonized transparent clock, the transparent clock requires physical layer frequency based on the ITU-T G.8262/.1 standard. To set syntonized transparent clock, you can enable Synchronous Ethernet configuration with Ethernet Synchronization Message Channel (ESMC) along with PTP transparent clock configuration. Syntonization supports frequency synchronization but does not support phase or time synchronization.

Note:

You might notice higher latency when you use copper SFP ports instead of fiber SFP ports. In this case, you must compensate the latency introduced by the copper SFP ports for the accurate CF (correction factor) measurement.

Platform-Specific Transparent Clock Behavior

Use Feature Explorer to confirm platform and release support for specific features.

Use the following table to review platform-specific behaviors for your platform:

Platform	Difference
ACX Series	ACX6360-OR devices support PTP over IPv6 for transparent clocks. ACX6360-OR devices do not support the following: Boundary, ordinary, timeTransmitter, and timeReceiver clocks Transparent clock over MPLS switched path Transparent clock with more than two VLAN tags PTP over Ethernet PTP over IPv4 PTP multicast mode Configuration of unicast and broadcast modes. Unicast mode is enabled by default. Transparent clock in transponder mode PTP while MACSec is enabled Two-step process ACX5048 and ACX5096 routers do not support the following: Boundary clock Ordinary clock Transparent clock over MPLS switched path Transparent clock with more than two VLAN tags PTP over IPv6 for transparent clocks. ACX5048 , ACX5096, and ACX6360-OR devices support only the one-step process, which means that the timestamps are sent in one packet.
EX Series	On EX4600, and EX4400 switches, PTP over Ethernet, IPv4, IPv6, unicast, and multicast for transparent clocks are supported. EX4300 and EX4300-MP switches do not support PTP transparent clock on virtual chassis mode.
PTX Series	PTX10001-36MR devices support PTP over IPv6 for transparent clocks. PTX10008 with the JNP10K-LC1301 line cards supports transparent clock feature. However, the following conditions apply: PTPoE, PTP over IPv4, and PTP over IPv6 encapsulations are supported. Transparent clock feature functions as expected only when the packets enter and leave through the JNP10K-LC1301 line cards. Timestamping does not work for PTP over IPV6 double tagged packets with L2 IFL and when the bridge domain is untagged.
QFX Series	PTP Transparent Clock is not supported on QFX5120-48YM device 1G ports. On QFX5100 switches, PTP over Ethernet, IPv4, IPv6, unicast, and multicast for transparent clocks are supported.