PHY Timestamping
The PHY timestamping refers to the timestamping of the IEEE 1588 event packets at the 1-Gigabit Ethernet and 10-Gigabit Ethernet PHY. Timestamping the packet in the PHY results in higher stability of recovered clock. The PHY timestamping updates the correction field of the packet.
Juniper Networks recommends that you configure timestamping at the physical layer if the port supports IEEE 1588 timestamping.
On 10-Gigabit Ethernet ports, PHY timestamping and WAN-PHY framing are mutually exclusive—that is, you cannot configure PHY timestamping on a 10-Gigabit Ethernet port if you have configured WAN-PHY framing mode on that port. This is applicable only for MPC5E and MPC6E with 24x10XGE MIC. PHY timestamping is not supported on the enhanced MPCs MPC1E, MPC2E, and MPC4E. Only hardware timestamping is supported on these MPCs. Therefore, a packet delay variation (also known as jitter) of up to 1 microsecond is observed on these MPCs for a very small percentage of packets occasionally. Hardware timestamping is typically timestamping either at FPGA or similar device.
On Junos Evo platforms, PHY timestamping is enabled by
default and the phy-timestamping configuration option is unavailable.
Platform-Specific PHY Timestamping Behavior
Use Feature Explorer to confirm platform and release support for specific features.
Use the following table to review platform-specific behaviors for your platform:
|
Platform |
Difference |
|---|---|
|
ACX Series |
ACX supports PHY timestamping in ordinary clock and boundary clock modes. |