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Scheduling on the Router Hardware, PIC, MIC, and MPC Interface Families

Table 1 compares the PIC, MIC, and MPC interface families with regard to scheduling abilities or features. Note that this table reflects the ability to perform the function at the PIC, MIC, or MPC interface level and not necessarily on the system as a whole.

Table 1: Scheduling on the Router Hardware and Interface Families Compared

Scheduling Feature:

MIC and MPC Interfaces

IQ PICs

IQ2 PICs

IQ2E PICs

Enhanced IQ PICs

Per–unit scheduling

Yes, for EQ MPC

Yes

Yes

Yes

Yes

Physical port and logical unit shaping

Yes

–

Yes

Yes

Yes

Guaranteed rate or peak rate support

Yes

–

Yes, supports both CIR and PIR on the same logical unit.

Yes

Yes, at the logical unit

Excess rate support

Yes

–

–

–

Yes, at the logical unit

Shared scheduler support

–

–

Yes

Yes

–