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show ptp global-information

Syntax

Description

Show Precision Time Protocol (PTP)–related global information.

Options

This command has no options.

Required Privilege Level

view

Output Fields

Table 1 lists the output fields for the show ptp global-information command. Output fields are listed in the approximate order in which they appear.

Table 1: show ptp global-information Output Fields

Field Name

Field Description

PTP Global Configuration

Displays if PTP is configured globally.

Domain Number

PTP domain with values from 0 through 127. The default value is 0. Only one PTP domain is supported at any given point in time.

Clock mode

Clock mode is either boundary or ordinary.

Profile Type

IEEE-2008, Enterprise, G.8275.1, G.8275.2.enh, SMPTE-ST 2059-2, AES67, and Combined AES67 and SMPTE-ST 2059-2.

Servo Type

Indicates whether the servo type applied on the platform is the default or the enhanced version.

Priority Level1

Priority value of the clock: 0 through 255. The default is 128. The lower value takes precedence.

Priority Level2

Priority value of the clock: 0 through 255. The default is 128. This value is used to differentiate and prioritize the primary clocks when the priority1-value is the same for different primary clocks in a network. The lower value takes precedence.

Unicast Negotiation

Method by which the announce, synchronization, and delay-response packet rates are negotiated between the primary and the client before a PTP session is established. Unicast negotiation is enabled or disabled.

ESMC QL From Clock Class

Denotes whether the conversion from clock class to QL is enabled or disabled.

Clock Class/ESMC QLl

Denotes the user defined clock class to QL conversion.

SNMP Trap Status

Denotes the SNMP trap generation status (Enabled or Disabled).

Master Parameters

Delay Request Timeout

The default value is 30 seconds. The range is from 30 to 300 seconds.

Transparent-clock-config

Displays if transparent clock mode is enabled or disabled.

Transparent-clock-status

Display the status of the transparent clock operation. The following status is as follows:

  • N/A—Transparent clock is not configured.

  • Active—Transparent clock is configured and working properly.

  • sync-in-progress—This is a temporary state. During startup, all the PHYs are synchronized with each other. This status also occurs when a new PIC is plugged in to the switch and all the PHYs go through the synchronization cycle again.

    Note:

    Transparent clock operation is disabled during the synchronization of PHYs.

  • Inactive—Transparent clock is configured but not working properly. This indicates a hardware error in PHY timestamping logic.

Syntonized transparent-clock-config

Displays if syntonized transparent clock mode is enabled or disabled.

PPM Status

Displays the Passive Port Monitoring (PPM) status (Enabled or Disabled) (only on PTX10004, PTX10008 devices).

PPM Delay Request Interval

PPM delay request interval supporting G.8275.1 specifications. The default value is -4, or (only on PTX10004, PTX10008 devices).

Syntonized transparent-clock-status

Display the status of the syntonized transparent clock operation. The following status is as follows:

  • N/A—Syntonized transparent clock is not configured.

  • Active—Syntonized transparent clock is configured and working properly.

  • sync-in-progress—This is a temporary state. During startup, all the PHYs are synchronized with each other. This status also occurs when a new PIC is plugged into the switch and all the PHYs go through the synchronization cycle again.

    Note:

    Syntonized transparent clock operation is disabled during the synchronization of PHYs.

  • Inactive—Syntonized transparent clock is configured but not working properly. This indicates a hardware error in PHY timestamping logic.

UTC Leap Seconds

The number of UTC leap seconds is 37 seconds by default. However, you can configure a different value.

Phase adjust threshold

Displays the maximum phase offset in nanoseconds that is adjusted by the G.8275.2 enhanced servo in a phase-aligned state. A higher phase adjust threshold permits a clock to tolerate phase offset changes because of higher network packet delay variation (PDV).

Note:

This field is displayed for supported platforms.

Frequency lock threshold

Displays the frequency offset in parts per billion (ppb) that the servo locks with. Locking with a higher frequency lock threshold allows a quicker frequency lock, although at the expense of a higher phase offset per window in the phase-aligned state.

Note:

This field is displayed for supported platforms.

Phase lock threshold

Displays he maximum phase offset in nanoseconds with which G.8275.2 enhanced servo enters the phase-aligned state. Phase locking with a higher phase lock threshold leads to the servo and time receiver getting into the phase-aligned state quickly.

Note:

This field is displayed for supported platforms.

Sample Output

show ptp global-information (Transparent Clock Configured)

show ptp global-information (Syntonized Transparent Clock Configured)

show ptp global-information (Default Profile)

show ptp global-information (Enterprise Profile)

show ptp global-information (G.8275.1 Profile)

show ptp global-information (G.8275.2.enh Profile)

show ptp global-information (MX10008, ACX7100-32C, ACX7100-48L and ACX7024)

show ptp global-information (SMPTE ST-2059-2 Profile)

show ptp global-information (AES67 Profile)

show ptp global-information (Combined AES67 and SMPTE ST-2059-2 Profile)

show ptp global-information (PTX10004, PTX10008 Devices)

Release Information

Command introduced in Junos OS Release 14.1X53-D25.

Output showing Syntonized Transparent Clock added in Junos OS Evolved Release 21.1R1.

SMPTE-ST 2059-2, AES67, and Combined AES67, and SMPTE-ST 2059-2 profile types are added in Junos OS Release 21.3 R1.

Frequency lock threshold, phase adjust threshold, and phase lock threshold output fields added in Junos OS Release 23.4R1 for MX10008.

Frequency lock threshold, phase adjust threshold, and phase lock threshold output fields supported for ACX7100-32C, ACX7100-48L, and ACX7024 in Junos OS Evolved Release 24.2R1.