Technical Documentation

Maximum Delay Buffer with q-pic-large-buffer Statement Enabled

Table 1 lists the maximum delay buffer that can be configured for T1, E1, and DS0 interfaces configured on Channelized IQ PICs:

Table 1: Maximum Delay Buffer with q-pic-large-buffer Statement Enabled

Platform, PIC, or Interface Type

Maximum Buffer Size

With Large Buffer Sizes Not Enabled

T Series and M320 routers

50,000 microseconds

Other M Series routers

200,000 microseconds

IQ PICs on all routers

100,000 microseconds

Channelized T1/E1 interface on J Series Services Routers

400,000 microseconds

With Large Buffer Sizes Enabled

Channelized T3 and channelized OC3 DLCIs—Maximum sizes vary by shaping rate:

With shaping rate from 64,000 through 255,999 bps

4,000,000 microseconds

With shaping rate from 256,000 through 511,999 bps

2,000,000 microseconds

With shaping rate from 512,000 through 1,023,999 bps

1,000,000 microseconds

With shaping rate from 1,024,000 through 2,048,000 bps

500,000 microseconds

With shaping rate from
2,048,001 bps through 10 Mbps

400,000 microseconds

With shaping rate from
10,000,001 bps through 20 Mbps

300,000 microseconds

With shaping rate from
20,000,001 bps through 30 Mbps

200,000 microseconds

With shaping rate from
30,000,001 bps through 40 Mbps

150,000 microseconds

With shaping rate up to 40,000,001 bps or higher

100,000 microseconds

NxDS0 IQ Interfaces—Maximum sizes vary by channel size:

1xDSO through 3xDS0

4,000,000 microseconds

4xDSO through 7xDS0

2,000,000 microseconds

8xDSO through 15xDS0

1,000,000 microseconds

16xDSO through 32xDS0

500,000 microseconds

Other IQ interfaces

500,000 microseconds


Published: 2010-04-26