Technical Documentation

Example: Configuring Channelized T3 IQ Interfaces

Configure a channelized T3 interface as an unpartitioned, clear channel.

Configuring a T3 Interface

[edit interfaces]ct3-5/0/0 {no-partition interface-type t3;}

Configuring NxDS0 and T1 Interfaces

Figure 1 shows the following interfaces on a Channelized DS3 IQ or IQE PIC:

  • A channelized T1, which is partitioned into NxDS0 interfaces
  • T1 interfaces

Figure 1: Sample Channelization of DS3 IQ or IQE PIC

Image g003015.gif

[edit interfaces]ct3-1/1/0 {description “CT3 to CT1 and CT3 to T1.”;t3-options {loopback remote;looptiming;}partition 1 interface-type ct1; # ct1-1/1/0:1.partition 2-28 interface-type t1; # t1-1/1/0:[2-28]}ct1-1/1/0:1 {description “case (a) CT1s to NxDSOs.”;t1-options {bert-algorithm all-ones-repeating;framing sf;line-encoding ami;}partition 1 timeslots 2 - 10 interface-type ds0; # ds-1/1/0:1:1, channel group with 10 DS0spartition 2 timeslots 11- 23 interface-type ds0; # ds-1/1/0:1:2, channel group with 13 DS0s...}

Published: 2010-04-20