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    Determine PCG Mastership

    The PCGs function as redundant components. For information about monitoring redundant PCGs, see Checklist for Monitoring Redundant PCGs.

    To determine which PCG is operating as the master:

    1. Display the PCG Master in the Craft Interface Output
    2. Check the PCG LED States for PCG Mastership on the Faceplate
    3. Display the Packet Forwarding Engine Current Clock Source

    Display the PCG Master in the Craft Interface Output

    Purpose

    To display the PCG master in the craft interface output.

    Action

    To determine the PCG master from the craft interface status information, use the following command:

    user@host> show chassis craft-interface

    Sample Output

    user@host> show chassis craft-interface
    [...Output truncated...]
    PCG LEDs:
      PCG  0   1
    --------------
    Amber  .   .
    Green  *   *
    Blue   *   .
    [...Output truncated...]
    

    Meaning

    The command output shows that PCG 0 is the master because the blue MASTER LED is on.

    Check the PCG LED States for PCG Mastership on the Faceplate

    Purpose

    To determine the PCG mastership from the PCG LEDs on the faceplate.

    Action

    To check the PCG LEDs, look on the PCG faceplate at the rear of the M40e or M160 router chassis (see PCG Overview). If the blue MASTER LED on the PCG faceplate is on steadily, the PCG is functioning as master (see Check the PCG LED States on the Faceplate).

    Display the Packet Forwarding Engine Current Clock Source

    Purpose

    The Packet Forwarding Engine current clock source is the master PCG.

    Action

    To display the PCG master from the Packet Forwarding Engine clock source output, use the following command:

    user@host> show chassis clocks

    Sample Output

    user@host> show chassis clocks
    PFE clock status:
      Current source            PCG 0
      Measured frequency        125.03 MHz
    Reference clock status:
      Current source            Primary
      Primary source            Internal
      Secondary source          Internal
      Tertiary source           Internal
      Rollover algorithm        Holdover
      PLL mode                  Free-running
      PLL errors                0
      Sync message current      0x00
      Sync message normal       0x00
      Sync message override     0x00 
    

    Meaning

    The command output shows that the PCG in slot 0 is the primary clock source.

     

    Related Documentation

     

    Published: 2012-08-20