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ATM2 OC12/STM4 IQ PIC (M7i Router)

 

Software release

  • Junos OS Release 6.0 and later

Description

  • One OC12 port

  • Power requirement: 0.41 A @ 48 V (20 W)

  • Intelligent queuing (IQ) PICs support fine-grained queuing per logical interface

  • Conforms to ANSI T1.105-1991 and T1E1.2/93-020R1

  • Complies with ATM and SONET/SDH standards

  • Alarm and event counting and detection

  • Compatible with well-known ATM switches

  • ATM switch ID, which displays the switch IP address and local interface name of the adjacent Fore ATM switches

Hardware features

  • One 3010 SAR for segmentation and reassembly into 53-byte ATM cells

  • High-performance parsing of SONET/SDH frames

  • ASIC-based packet segmentation and reassembly (SAR) management and output port queuing

  • 64 MB SDRAM memory for ATM SAR

  • Packet buffering, Layer 2 parsing

Software features

  • Circuit cross-connect for leveraging ATM access networks

  • User-configurable virtual circuit (VC) and virtual path (VP) support

  • Support for idle cell or unassigned cell transmission

  • OAM fault management processes alarm indication signal (AIS), remote defect indication (RDI), and loop cells

  • Point-to-point and point-to-multipoint mode Layer 2 counters per VC and per VP

  • Local and remote loopback

  • ATM Inverse ARP, which enables routers to automatically learn the IP address of the router on the far end of an ATM PVC

  • Simple Network Management Protocol (SNMP):

    • Management Information Base (MIB) 2 (RFC 1213)

    • ATM MIB (RFC 1695)

    • SONET MIB

  • Unspecified bit rate (UBR), non-real-time variable bit rate (VBR), and constant bit rate (CBR) traffic shaping

  • Per-VC or per-VP traffic shaping

  • Support for F4 OAM cells

  • Support for 16-bit VCI range

Cables and connectors

LEDs

One tricolor per port:

  • Off—Not enabled

  • Green—Online with no alarms or failures

  • Yellow—Online with alarms for remote failures

  • Red—Active with a local alarm; router has detected a failure

Alarms, errors, and events

  • Alarm indication signal (AIS-L, AIS-P)

  • Bit error rate signal degrade (BERR-SD), bit error rate signal fail (BERR-SF)

  • Bit interleaved parity errors B1, B2, B3

  • Errored seconds (ES-S, ES-L, ES-P), far-end bit errors REI-L, REI-P (CV-LFE, CV-PFE), far-end errored seconds (ES-LFE, ES-PFE), far-end severely errored seconds (SES-LFE, SES-PFE), far-end unavailable seconds (UAS-LFE, UAS-PFE)

  • Loss of cell delineation (LOC), loss of frame (LOF), loss of pointer (LOP-P), loss of signal (LOS)

  • Payload mismatch (PLM-P), payload unequipped (UNEQ-P)

  • Remote defect indication (RDI-L, RDI-P)

  • Severely errored framing (SEF), severely errored framing seconds (SEFS-S), severely errored seconds (SES-S, SES-L, SES-P), unavailable seconds (UAS-L, UAS-P)