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    Data Flow Through a T-series Routing Platform

    Figure 1 illustrates the data flow through a T640 routing node. In this example, data flows in the following sequence:

    1. Packets enter through an incoming PIC and are passed to the Packet Forwarding Engine on the originating FPC.
    2. The Layer2/Layer 3 Packet Processing ASIC parses the packets and divides them into cells. In addition, the behavior aggregate (BA) classifier determines the forwarding treatment for each packet.

    Figure 1: Data Flow Through a T640 Routing Node

    Data Flow Through a T640 Routing Node
    1. The network-facing Switch Fabric ASIC places the lookup key in a notification and passes it to the T-series Internet Processor.
    2. The Switch Fabric ASIC also passes the data cells to the Queuing and Memory Interface ASICs for buffering on the FPC.
    3. The T-series Internet Processor performs the route lookup and forwards the notification to the Queuing and Memory Interface ASIC. In addition, if configured filtering, policing, sampling and mulitfield classification, are performed at this time.
    4. The Queuing and Memory Interface ASIC sends the notification to the switch-fabric-facing Switch Interface ASIC, which sends bandwidth requests through the switch fabric to the destination port, and issues read requests to the Queuing and Memory Interface ASIC to begin reading data cells out of memory.
    5. The Switch Interface ASIC on the destination FPC sends bandwidth grants through the switch fabric to the originating Switch Interface ASIC.
    6. Upon receipt of each grant, the originating Switch Interface ASIC sends a cell through the switch fabric to the destination Packet Forwarding Engine.
    7. On the destination Packet Forwarding Engine, the switch-fabric-facing Switch Interface ASIC receives the data cells, places the lookup key in a notification, and forwards the notification to the T-series Internet Processor.
    8. The T-series Internet Processor performs the route lookup and forwards the notification to the Queuing and Memory Interface ASIC, which forwards it to the network-facing Switch Interface ASIC.
    9. The Switch Interface ASIC sends requests to the Queuing and Memory Interface ASIC to read the data cells out of memory, and passes the cells to the Layer2/Layer 3 Packet Processing ASIC, which reassembles the cells into packets, performs the necessary Layer 2 encapsulation, and sends the packets to the outgoing PIC. Queueing policy and rewrites occur at this time on the egress router.
    10. The PIC passes the packets into the network.

    For more information about the M-series routers and T-series platforms, see the router platform-specific hardware guide, and the Junos Hardware Network Operations Guide.

    Published: 2015-05-10