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Home > Support > Technical Documentation > JunosE Software > Configuring the Capability to Detect Corruption in the FPGA Statistics for Policies Managed by the SRC Software
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Related Documentation

  • Detection of Corruption in the FPGA Statistics for Policies of Subscribers Managed by the SRC Software
  • Computation of the Interface and Policy Counters for the Detection of Corruption in the FPGA Statistics
  • Example: Computation of the Threshold Value by Using Interface and Policy Counters for the Detection of Corruption in the FPGA Statistics
  • Scenarios for the Detection of Corruption in the FPGA Statistics and the Determination of the Threshold
  • Monitoring the Detection of Corrupted FPGA Statistics Settings
 

Configuring the Capability to Detect Corruption in the FPGA Statistics for Policies Managed by the SRC Software

You can configure the router, which functions as an SRC client, to perform a validation of the FPGA statistics and identify any corruption in the statistical values that are computed based on interface and policy counters in the output of the show ip interface or show ipv6 interface commands. You must enable the capability to check the FPGA statistics for corruption and also specify a threshold value, exceeding which the FPGA statistics is determined to be defective. In such a scenario, you can prevent the SRC client from sending incorrect and discrepant statistics to the SRC server because of hardware corruption.

To configure the capability to check for corruption in the FPGA statistics for policies managed by the SRC server:

  1. Enable the detection functionality to identify inaccuracies in the FPGA statistics before the counter values are reported to the SRC server during a COPS session.
    host#fpga-stats-monitoring-enable

    By default, the functionality to detect corruption in the FPGA statistics is disabled. Use the no version of this command to disable this functionality.

  2. Specify a threshold value that is used as a checkpoint to determine whether the FPGA statistics is corrupted. The threshold is the maximum permissible deviation between interface and policy counter values. If the threshold is higher than the difference between the interface and policy counters, no corruption has occurred in the FPGA statistics. If the threshold is lower than the difference between the interface and policy counters, corruption has occurred in the FPGA statistics.
    host1(config)# fpga-stats-monitoring threshold 40 

    In this example, the threshold value is set as 40. If the difference between the interface counters and policy counters for ingress or egress policies collected over two polling intervals equals or exceeds 40, a corruption is detected in the FPGA statistics and the subscriber statistics are not forwarded to the SRC server. If the difference between the interface counters and policy counters for ingress or egress policies collected over two polling intervals is less than 40, no corruption is identified in the FPGA statistics and the collected subscriber statistical details are sent to the SRC server.

 

Related Documentation

  • Detection of Corruption in the FPGA Statistics for Policies of Subscribers Managed by the SRC Software
  • Computation of the Interface and Policy Counters for the Detection of Corruption in the FPGA Statistics
  • Example: Computation of the Threshold Value by Using Interface and Policy Counters for the Detection of Corruption in the FPGA Statistics
  • Scenarios for the Detection of Corruption in the FPGA Statistics and the Determination of the Threshold
  • Monitoring the Detection of Corrupted FPGA Statistics Settings
 

Published: 2012-07-03

 
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