ATM Integrated Scheduler Overview

The E Series Broadband Services Router provides extended ATM QoS functionality through its integrated scheduler. The integrated scheduler consists of two schedulers in series—the hierarchical round robin (HRR) scheduler and the segmentation and reassembly (SAR) scheduler.

The integrated scheduler enables you to configure QoS on your ATM networks using the HRR scheduler that is used on all E Series ASIC-enabled line modules. In addition, you can use the commercial SAR scheduler to configure traditional ATM cell-based QoS.

Note: The term HRR scheduler is used in this chapter to describe the scheduling performed by the ASIC on the ATM line module. Although the ASIC might differ depending on the ATM line module, the configuration and performance of the HRR scheduler are the same. For example, the ERX7xx models, ERX14xx models, and ERX310 Broadband Services router use the egress forwarding ASIC (EFA); and the E120 and E320 Broadband Services Routers use the frame forwarding ASIC (FFA) on the ES2 4G LM.

The HRR scheduler and the SAR scheduler work together as an integrated scheduler for ATM traffic. The HRR scheduler is configured by default with per-VC and per-IP interface scheduler nodes, and one best-effort class queue for each IP interface. The SAR scheduler implements weighted round-robin scheduling with one queue per VC. The VC queues are grouped into round robins based on the ATM service classes and the VP tunnels you have configured.

In the default integrated mode, controlled by the ATM application, the SAR scheduler controls the scheduling via the VC backpressure messages it sends to the HRR scheduler. When the HRR scheduler receives a backpressure message from the SAR scheduler, the HRR scheduler disables the node regardless of the node weight or shaping rate. When the HRR scheduler receives a backpressure release, the scheduler node is reenabled.

Backpressure and the Integrated Scheduler

ATM packets are initially scheduled through the HRR scheduler and then sent to the SAR scheduler, from where the cells are scheduled onto the circuit. If a SAR VC queue begins to fill up, the SAR scheduler issues VC backpressure messages to the HRR scheduler. The backpressure messages control the amount of traffic the HRR scheduler sends to the SAR scheduler. The SAR scheduler can also exert port backpressure on the HRR scheduler.

In default integrated mode, the SAR sends VC backpressure messages as well as port backpressure messages. Port backpressure messages are sent to the port node in the hierarchical scheduler.

Backpressure is a critical mechanism that enables the two schedulers in series to operate as a single integrated scheduler. Backpressure ensures that packets do not drain over internal data paths at an unmanageable rate from the HRR scheduler to the SAR scheduler. Without backpressure from the SAR scheduler, the HRR scheduler does not detect congestion even if the SAR scheduler is completely saturated.

Note: The default QoS profile for ATM (atm-default) contains the atm-vc node command, which creates the scheduler node that is required by the SAR VC backpressure mechanism. If the SAR scheduler is operating in default integrated mode, this command must be in QoS profiles that are attached to ATM ports.

Figure 1 shows the HRR and SAR schedulers working together to form the integrated scheduler. When the SAR VC queues start to back up, the SAR exerts VC backpressure to the corresponding VC node in the HRR scheduler.

VC backpressure affects only VC nodes that are in the default traffic-class group. As a consequence, VC nodes that are in named traffic-class groups within the scheduler hierarchy are not affected by VC backpressure.

Figure 1: Integrated ATM Scheduler

In a WAN field programmable gate array (FPGA), the backpressure to the IOA is generated from the system packet interface (SPI4) first-in, first-out (FIFO) queue buffers that are partially full. An intermediate FIFO exists between the SIO from the IOA and the SPI4 to the storage router accelerator (SRA) or Internet eXchange processor (IXP). The SRA on an ES2 10G line module is almost identical to the ES2 10G Uplink line module, with the exception that the ES2 10G LM contains an SRA, its associated memory, and a utility FPGA. When the intermediate FIFO becomes full to half its total capacity, it sets an overflow that stops transmission of packets to the SPI4 and waits for the next End of Packet (EOP) bit before sending the next packet. This mechanism sends an out-of-sequence bit to the SPI4. Therefore, the intermediate FIFO becomes full to half its total size always on systems that display SRA1 when the WAN status registers are read.

The following enhancements have been made to the WAN FPGA:

• The FIFO buffer has been enlarged by 4 times its previous size.
• When the FIFO buffer is 5/8 full, backpressure is sent to the IOA.
• When the FIFO buffer is 3/4 full, an overflow is set, an error is sent and an EOP is generated before the stoppage of transmission of packets to the SPI4. This method of processing causes the interface to receive a valid protocol.
• The error registers in the WAN FPGA of ES2 10G ADV LMs are correctly adjusted with the error data widths of the V5 serial input/output (SIO) status registers.

VP Shaping

VP shaping can be performed either in the SAR or by using the QoS shaping application using QoS profiles. Configuring VP shaping in the SAR enables traffic to be sent out of the port at a rate that closely matches strict ATM contract rates. SAR VP shaping is configured for the physical port using the atm vp-tunnel command.