Packet Forwarding Engine Architecture

The Packet Forwarding Engine performs Layer 2 and Layer 3 packet switching. It can forward up to 40 for all packet sizes. The aggregate throughput for the router is 6.4 gigabits per second (Gbps), full duplex. The Packet Forwarding Engine is implemented in application-specific integrated circuits (ASICs). It uses a centralized route lookup engine and shared memory.

The Packet Forwarding Engine architecture includes the following components:

• Midplane—Transports packets, notifications, and other signals between the PICs and the Packet Forwarding Engine (as well as other system components).
• Physical Interface Card (PIC)—Physically connects the router to fiber-optic or digital network media. A controller ASIC in each PIC performs control functions specific to the PIC media type.
• Forwarding Engine Board (FEB)—Hosts the Internet Processor II ASIC, I/O Manager ASIC (one on the M5 router, two on the M10 router), and two Distributed Buffer Manager ASICs. An I/O Manager ASIC divides incoming packets into 64-byte data cells and reassembles cells into data packets for transmission on the network after the Internet Processor II ASIC decides how to forward the packets. One Distributed Buffer Manager ASIC distributes the data cells among the memory buffers on the FEB and the other notifies the PICs of the forwarding decision for outgoing packets.

Data Flow through the Packet Forwarding Engine

Use of ASICs promotes efficient movement of data packets through the system. Packets flow through the Packet Forwarding Engine in the following sequence (see Figure 13):

1. Packets arrive at an incoming PIC interface.
2. The PIC passes the packets through the midplane to the FEB.
3. An I/O Manager ASIC on the FEB processes the packet headers and divides the packets into 64-byte data cells.
4. A Distributed Buffer Manager ASIC on the FEB distributes the data cells throughout the memory buffers on the FEB.
5. The Internet Processor II ASIC on the FEB performs a route lookup for each packet and decides how to forward it.
6. The Internet Processor II ASIC notifies the second Distributed Buffer Manager ASIC of the forwarding decision, and the Distributed Buffer Manager ASIC forwards the notification to the appropriate outbound PIC.
7. The I/O Manager ASIC on the FEB reassembles data cells stored in shared memory into data packets as they are ready for transmission and passes them to the outbound PIC.
8. The outbound PIC transmits the data packets.

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