Packet Forwarding Engine Architecture
The Packet Forwarding Engine performs Layer 2 and Layer 3 packet switching. It can forward up to 40 million packets per second for all packet sizes, which exceeds the line speed of eight OC-48/STM-16 lines. The aggregate throughput for the router is 40 gigabits per second (Gbps) simplex or 2.5 Gbps per FPC installed in the system. The Packet Forwarding Engine is implemented in application-specific integrated circuits (ASICs). It uses a centralized route lookup engine and shared memory.
Packet Forwarding Engine includes the following components (see Figure 12):
- Physical Interface Cards (PICs)—Physically connect the router to a complete range of fiber-optic and digital network media. A controller ASIC in each PIC performs control functions specific to the PIC media type.
- Flexible PIC Concentrators (FPCs)—House PICs and provide shared memory for processing incoming and outgoing packets. Each FPC hosts an I/O Manager ASIC, which divides incoming data packets into memory blocks (cells) and reassembles the cells into data packets when they are ready for transmission.
- Backplane—Transports packets, notifications, and other signals between the FPCs and the SCB (as well as other system components). Hosts the Distributed Buffer Manager ASIC, which distributes incoming data cells to the shared memory buffers on the FPCs and notifies the FPCs of forwarding decisions for outgoing packets.
- System Control Board (SCB)—Hosts the Internet Processor or Internet Processor II ASIC, which makes forwarding decisions.
