System and Switch Board (SSB)

The System and Switch Board (SSB) performs route lookup, filtering, and switching on incoming data packets, then directs outbound packets to the appropriate FPC for transmission to the network. It can process 40 million packets per second (Mpps).

One or two SSBs can be installed into the uppermost slots in the front of the chassis, as shown in Figure 1. Only one SSB is active at a time, with the optional second SSB in reset mode. SSBs are hot-pluggable, as described in Field-Replaceable Units (FRUs). Removing the standby SSB has no effect on router function. If the active SSB fails or is removed from the chassis, the effect depends on whether two SSBs are installed:

• If there is only one SSB, forwarding halts until the SSB is replaced and functioning again.
• If there are two SSBs, forwarding halts until the standby SSB boots and becomes active.

In both cases, all components in the Packet Forwarding Engine reset, and it takes approximately one minute for the new SSB to become active; synchronizing router configuration information can take additional time, depending on the complexity of the configuration.

For SSB replacement instructions, see Replacing an SSB.

The SSB communicates with the Routing Engine using a dedicated 100-Mbps Fast Ethernet link that transfers routing table data from the Routing Engine to the forwarding table in the Internet Processor II ASIC. The link is also used to transfer from the SSB to the Routing Engine routing link-state updates and other packets destined for the router that have been received through the router interfaces.

The ASICs and other components on the SSB provide the following functions:

• Route lookups—The Internet Processor II ASIC on each SSB performs route lookups using the forwarding table stored in SSRAM.
• Management of shared memory on the FPCs—One Distributed Buffer Manager ASIC receives the 64-byte data cells into which the I/O Manager ASIC on each FPC divides incoming packets, and uniformly allocates them throughout the shared memory buffers located on the FPCs.
• Transfer of outgoing data packets—The second Distributed Buffer Manager ASIC passes notification of the forwarding decision for each packet to an I/O Manager ASIC so that data cells for the outgoing packet can be reassembled for transmission to the network.
• Transfer of exception and control packets—The Internet Processor II ASIC passes exception packets to the microprocessor on the SSB, which processes almost all of them. The SSB sends any remaining exception packets to the Routing Engine for further processing. When the SSB detects an error originating in the Packet Forwarding Engine, it sends it to the Routing Engine using system logging (syslog) messages.
• Monitoring of system components—The SSB monitors other system components for failure and alarm conditions. It collects statistics from all sensors in the system and relays them to the Routing Engine, which sets alarms as appropriate. For example, if the temperature of a component exceeds the lower of two internally defined thresholds, the Routing Engine issues a “high temperature” alarm. If the temperature exceeds the higher threshold, the Routing Engine initiates a system shutdown.
• Controlling FPC resets—The SSB monitors the operation of the FPCs. If it detects errors in an FPC, the SSB attempts to reset the FPC. After three unsuccessful resets, the SSB takes the FPC offline and informs the Routing Engine. Other FPCs are unaffected, and normal system operation continues.
• Providing SONET/SDH clock source—The SSB generates a 19.44-MHz clock signal for use by SONET/SDH interfaces.

SSB Components

An SSB has the following components (see Figure 12 and Figure 13):

• Two Distributed Buffer Manager ASICs—Process incoming and outgoing packets: one distributes data cells (which the I/O Manager ASIC on each FPC derives from incoming packets) to the shared memory buffers on the FPCs, while the second forwards notification of routing decisions to the I/O Manager ASICs.
• One Internet Processor II ASIC—Performs route lookups and makes routing decisions.
• Parity-protected SSRAM—Stores the forwarding table.
• Processor subsystem—Manages SSB functions and handles exception packets. The processor has the following components:
  • One PowerPC 603e processor
  • Parity-protected Level 2 cache
  • Parity-protected DRAM
• EEPROM—Stores the serial number and revision level.
• Offline button—Prepares the SSB for removal from the router when pressed.
• 19.44-MHz stratum 3 reference clock—Generates clock signal for SONET/SDH PICs.
• I²C controller—Monitors the status of router components.
• Debug port—Connects the SSB to a laptop or other monitoring device through an RS-232 (EIA-232) serial cable. It uses a DB-25 connector. See Figure 13.
• Five LEDs—Indicate SSB status. There are two green ones labeled STATUS, an amber one labeled OFFLINE, a green one labeled ONLINE, and a green one labeled MASTER. Table 10 describes the LED states.
• Ejector levers—Control the locking system that secures the SSB in the chassis.

Note: For specific information about SSB components (for example, the amount of DRAM), issue the show chassis ssb command.

Figure 12: System and Switch Board

Figure 13: SSB Faceplate

Table 10: States for SSB LEDs