Packet Forwarding Engine Architecture

The Packet Forwarding Engine performs Layer 2 and Layer 3 packet switching. It can forward up to 40 Mpps for all packet sizes. The aggregate throughput is 3.2 gigabits per second (Gbps) per FPC. The Packet Forwarding Engine is implemented in application-specific integrated circuits (ASICs). It uses a centralized route lookup engine and shared memory.

The Packet Forwarding Engine architecture includes the following components:

• Midplane—Transports packets, notifications, and other signals between the FPCs and the Packet Forwarding Engine (as well as other system components).
• Physical Interface Card (PIC)—Physically connects the router to fiber-optic or digital network media. A controller ASIC in each PIC performs control functions specific to the PIC media type.
• Flexible PIC Concentrators (FPCs)—House PICs and provide shared memory for processing incoming and outgoing packets. Each FPC hosts an I/O Manager ASIC, which divides incoming data packets into memory blocks (cells) and reassembles the cells into data packets when they are ready for transmission.
• System and Switch Board (SSB)—Hosts an Internet Processor II ASIC, which makes forwarding decisions, and two Distributed Buffer Manager ASICs: one distributes data cells to the shared memory buffers on the FPCs and the other notifies the FPCs of forwarding decisions for outgoing packets.

Data Flow Through the Packet Forwarding Engine

Use of ASICs promotes efficient movement of data packets through the system. Packets flow through the Packet Forwarding Engine in the following sequence (see Figure 21):

1. Packets arrive at an incoming PIC interface.
2. The PIC passes the packets to the I/O Manager ASIC on the FPC.
3. The I/O Manager ASIC processes the packet headers, divides the packets into 64-byte data cells, and passes the cells through the midplane to the SSB.
4. A Distributed Buffer Manager ASIC on the SSB distributes the data cells throughout the memory buffers located on and shared by all the FPCs.
5. The Internet Processor II ASIC on the SSB performs a route lookup for each packet and decides how to forward it.
6. The Internet Processor II ASIC notifies a Distributed Buffer Manager ASIC (on the SSB) of the forwarding decision, and the Distributed Buffer Manager ASIC forwards the notification to the FPC that hosts the appropriate outbound interface.
7. The I/O Manager ASIC on the FPC reassembles data cells stored in shared memory into data packets as they are ready for transmission and passes them to the outbound PIC.
8. The outbound PIC transmits the data packets.

Figure 21: Packet Forwarding Engine Components and Data Flow