Packet Forwarding Engine Architecture

The Packet Forwarding Engine performs Layer 2 and Layer 3 packet switching. It can forward up to 160 for all packet sizes. The aggregate throughput for the router is 160 gigabits per second (Gbps) simplex or 80 Gbps full duplex. The Packet Forwarding Engine is implemented in application-specific integrated circuits (ASICs). It uses a centralized route lookup engine and shared memory.

The Packet Forwarding Engine architecture includes the following components:

• Midplane—Transports packets, notifications, and other signals between the FPCs and the Packet Forwarding Engine (as well as other system components).
• Physical Interface Card (PIC)—Physically connects the router to fiber-optic or digital network media. A controller ASIC in each PIC performs control functions specific to the PIC media type.
• Flexible PIC Concentrator (FPC)—Houses PICs and provides shared memory for processing incoming and outgoing packets. Each FPC hosts four I/O Manager ASICs, which divide incoming data packets into memory blocks (cells) before passing them to the SFMs, and reassembles cells into data packets when the packets are ready for transmission. The FPC also hosts two Packet Director ASICs—one distributes incoming packets among the I/O Manager ASICs, and the other distributes outgoing packets to the appropriate PICs on the FPC.
• Switching and Forwarding Module (SFM)—Hosts an Internet Processor II ASIC, which makes forwarding decisions, and two Distributed Buffer Manager ASICs: one distributes data cells to the shared memory buffers on the FPCs and the other notifies the FPCs of forwarding decisions for outgoing packets.

Data Flow through the Packet Forwarding Engine

Use of ASICs promotes efficient movement of data packets through the system. Packets flow through the Packet Forwarding Engine in the following sequence (see Figure 23):

1. Packets arrive at an incoming PIC interface.
2. The PIC passes the packets to the FPC, where the Packet Director ASIC distributes them among the I/O Manager ASICs.
3. The I/O Manager ASICs process the packet headers, divide the packets into 64-byte data cells, and pass the cells through the midplane to the SFMs.
4. The Distributed Buffer Manager ASICs on the SFMs distribute the data cells throughout memory buffers located on and shared by all the FPCs.
5. For each packet, an Internet Processor II ASIC on an SFM performs a route lookup and decides how to forward the packet.
6. The Internet Processor II ASIC notifies a Distributed Buffer Manager ASIC of the forwarding decision, and the Distributed Buffer Manager ASIC forwards the notification to the FPC that hosts the appropriate outbound interface.
7. The I/O Manager ASIC on the FPC reassembles data cells in shared memory into data packets as they are ready for transmission and passes them through the Packet Director ASIC to the outbound PIC.
8. The outbound PIC transmits the data packets.