Scheduling on the Router Hardware and PIC Families
Table 1 compares the PIC families with regard to scheduling abilities or features. Note that this table reflects the ability to perform the function at the PIC level and not necessarily on the system as a whole. In this table, the OSE PICs refer to the 10-port 10-Gigabit OSE PICs.
Table 1: Scheduling on Router Hardware and Interface Families Compared
Scheduling Feature: | M320 and T Series | Trio DPC/MPCs | IQ PICs | IQ2 PICs | IQ2E PICs | OSE PICs on T Series | Enhanced IQ PICs |
|---|---|---|---|---|---|---|---|
Per–unit scheduling | – | Yes, for EQ MPC | Yes | Yes | Yes | – | Yes |
Physical port and logical unit shaping | – | Yes | – | Yes | Yes | – | Yes |
Guaranteed rate or peak rate support | – | Yes | – | Yes | Yes | Yes, at the queue level | Yes, at the logical unit |
Excess rate support | – | Yes | – | – | – | Yes | Yes, at the logical unit |
Shared scheduler support | – | – | – | Yes | Yes | – | – |
