100-Gigabit Ethernet PIC Overview
The 100-Gigabit Ethernet PIC is a 1-port 100-Gigabit Ethernet Type 4 PIC with C form-factor pluggable (CFP) optics for T1600 routers with T1600-FPC4-ES and TX Matrix Plus routers. The 100-Gigabit Ethernet PIC must occupy FPC slots 0 and 1, requiring two slots. One T1600 router can support up to 8 100-Gigabit Ethernet PICs and up to 16 ports can be configured. Furthermore, the TX Matrix Plus router supports up to 128 100-Gigabit Ethernet PICs on a single multichassis routing node. Type 4 PICs can also be flexibly mixed with other FPC types to match high capacity platform requirements with existing configurations.
The 100-Gigabit Ethernet PIC supports flexible encapsulation and MAC accounting. MAC learning, MAC policing, and Layer 2 rewrite functionality are not supported.
The 100-Gigabit Ethernet PIC supports pluggable CFP optics for short reach (SR), extended reach (ER), and long reach (LR) applications, as per the CFP MSA definition. The optics identification, type information, and digital diagnostic management (DDM) are accessible using an MDIO bus. CFP optics support the following:
- 100GBASE-LR4: Long reach, SMF, 10km
- 100GBASE-ER4: Extended reach, SMF, 40km
- 100GBASE-SR10: Short reach, MMF, 100m
The ingress flow can be filtered based on the VLAN source and destination addresses. Ingress frames can also be classified according to VLAN, stacked VLAN, source address, VLAN source address, and stacked VLAN source address. VLAN manipulation on egress frames are supported on both outer and inner VLAN tags.
The following features are supported:
- The following encapsulation protocols are supported:
- Layer 2 protocols
- Ethernet CCC, Ethernet TCC, Ethernet VPLS
- VLAN CCC
- Extended VLAN TCC
- VLAN VPLS
- Flexible Ethernet service
- Layer 3 protocols
- IPv4
- Ipv6
- MPLS
- Layer 2 protocols
- CFP Multi-Source Agreement (MSA) compliant Management Data Input/Output (MDIO) control features (optics dependent).
- Graceful Routing Engine switchover (GRES) is supported in all PIC and chassis configurations.
- Interface creation:
- There are two physical interfaces when the 100-Gigabit Ethernet PIC is online (et-x/0/0:0 and et-x/0/0:1, where x represents the FPC slot number). Each physical interface represents two internal 50-Gigabit Ethernet Packet Forwarding Engines. Two logical interfaces are configured under each physical interface.
- Packet Forwarding Engine 0 is physical interface 0, Packet Forwarding Engine 1 is physical interface 1
- 802.3 link aggregation:
- Two logical interfaces are created for each 100-Gigabit Ethernet PIC. To utilize bandwidth beyond 50 gigabits per second, an aggregate interface must be explicitly configured on the 100-Gigabit Ethernet PIC that includes the two 50 gigabit interfaces.
- Each 100 gigabit Ethernet aggregate consumes one of the router-wide aggregated Ethernet device pools. The number of 100-Gigabit Ethernet PICs cannot exceed the router-wide limit, which is 128 for Ethernet.
- In each aggregate bundle, each 100-Gigabit Ethernet PIC consumes two members. Hence, an aggregate bundle that consists purely of 100-Gigabit Ethernet PICs supports a maximum of half of the software limit for the number of members. Therefore, with a maximum of 16 links, up to 8 100-Gigabit Ethernet links are supported.
- Software Packet Forwarding Engine—Supports all Gigabit Ethernet PIC classification, firewall filter, queuing model, and rewrite functionality.
- Egress traffic performance—Maximum egress throughput is 100 gigabits per second on the physical interface, with 50 gigabits per second on the two assigned logical interfaces.
- Ingress traffic performance—Maximum ingress throughput is 100 gigabits per second on the physical interface, with 50 gigabits per second on the two assigned logical interfaces.
- Interoperability—The 100-Gigabit Ethernet PICs support interconnection only with other Juniper Networks 100-Gigabit Ethernet PICs (Model: PD-1x100GE-CFP) interfaces. Interoperability with interfaces from other vendors is not supported.
