List of Tables

Table 1: Notice Icons

Table 2: Text and Syntax Conventions

Table 3: CoS Mappings—Inputs and Outputs

Table 4: Default VPLS Classifiers

Table 5: Default IP Precedence Classifier

Table 6: Default MPLS Classifier

Table 7: Default DSCP Classifier

Table 8: Default IEEE 802.1p Classifier

Table 9: Default IEEE 802.1ad Classifier

Table 10: Default IP Precedence (ipprec-default) Classifier

Table 11: Logical Interface Classifier Combinations

Table 12: Default MPLS EXP Classification Table

Table 13: Default CoS Values

Table 14: Policer Actions

Table 15: Color-Blind Mode TCM Color-to-PLP Mapping

Table 16: Color-Aware Mode TCM PLP Mapping

Table 17: Color-Blind Mode TCM Color-to-PLP Mapping

Table 18: Color-Aware Mode TCM Mapping

Table 19: Tricolor Marking Policer Statements

Table 20: Default Forwarding Classes

Table 21: Sample Forwarding Class-to-Queue Mapping

Table 22: Buffer Size Temporal Value Ranges by Router Type

Table 23: Recommended Delay Buffer Sizes

Table 24: Maximum Delay Buffer with q-pic-large-buffer Enabled by Interface

Table 25: Delay-Buffer Calculations

Table 26: NxDS0 Transmission Rates and Delay Buffers

Table 27: Scheduling Priority Mappings by FPC Type

Table 28: Shaping Rate and WRR Calculations by PIC Type

Table 29: Transmission Scheduling Support by Interfaces Type

Table 30: Bandwidth and Delay Buffer Allocations by Configuration Scenario

Table 31: Bandwidth and Delay Buffer Allocations by Configuration Scenario

Table 32: Scheduler Allocation for an Ethernet IQ2 PIC

Table 33: RTT Delay Buffers for IQ2 PICs

Table 34: Hierarchical Scheduler Nodes

Table 35: Queue Priority

Table 36: Internal Node Queue Priority for CIR Mode

Table 37: Internal Node Queue Priority for PIR-Only Mode

Table 38: Current Behavior with Multiple Priority Levels

Table 39: Current Behavior with Same Priority Levels

Table 40: Current Behavior with Strict-High Priority

Table 41: Strict-High Priority with Higher Load

Table 42: Sharing with Multiple Priority Levels

Table 43: Sharing with the Same Priority Levels

Table 44: Sharing with at Least One Strict-High Priority

Table 45: Sharing with at Least One Strict-High Priority and Higher Load

Table 46: Sharing with at Least One Strict-High Priority and Rate Limit

Table 47: Default Packet Header Rewrite Mappings

Table 48: Default MPLS EXP Rewrite Table

Table 49: CoS Hardware Capabilities and Limitations

Table 50: Drop Priority Classification for Packet Sent from Enhanced III to Enhanced II FPC on M320 Routers

Table 51: Drop Priority Classification for Packet Sent from Enhanced II FPC Without Tricolor Marking to Enhanced III FPC on M320 Routers

Table 52: Drop Priority Classification for Packet Sent from Enhanced II FPC with Tricolor Marking to Enhanced III FPC on M320 Routers

Table 53: Routing Engine Protocol Queue Assignments

Table 54: CoS Features of the Router Hardware and Interface Families Compared

Table 55: Scheduling on Router Hardware and Interface Families Compared

Table 56: Schedulers on the Router Hardware and Interface Families Compared

Table 57: Queue Parameters on the Router Hardware and Interface Families Compared

Table 58: Default Handling of Excess Traffic

Table 59: Basic Example of Excess Bandwidth

Table 60: Hardware Use of Basic Example Parameters

Table 61: Default Mode Example for IQE PICs

Table 62: Undersubscribed PIR Mode Example for IQE PICs

Table 63: Oversubscribed PIR Mode Example for IQE PICs

Table 64: CIR Mode Example for IQE PICs

Table 65: Excess Rate Mode Example for IQE PICs

Table 66: Default Queue Rates on the IQE PIC

Table 67: PIR Mode, with No Excess Configuration

Table 68: PIR Mode, with No Excess Hardware Behavior

Table 69: PIR Mode with Transmit Rate Configuration

Table 70: PIR Mode with Transmit Rate Hardware Behavior

Table 71: Second PIR Mode with Transmit Rate Configuration Example

Table 72: Second PIR Mode with Transmit Rate Hardware Behavior Example

Table 73: PIR Mode with Transmit Rate and Excess Rate Configuration

Table 74: PIR Mode with Transmit Rate and Excess Rate Hardware Behavior

Table 75: Excess Rate Configuration

Table 76: Excess Rate Hardware Behavior

Table 77: PIR Mode Generating Error Condition

Table 78: PIR Mode Generating Error Condition Behavior

Table 79: CIR Mode with No Excess Rate Configuration

Table 80: CIR Mode with No Excess Rate Hardware Behavior

Table 81: CIR Mode with Some Shaping Rates and No Excess Rate Configuration

Table 82: CIR Mode with Some Shaping Rates and No Excess Rate Hardware Behavior

Table 83: CIR Mode with Shaping Rates and Transmit Rates and No Excess Rate Configuration

Table 84: CIR Mode with Shaping Rates and Transmit Rates and No Excess Rate Hardware Behavior

Table 85: CIR Mode with Shaping Rates Greater Than Logical Interface Shaping Rate Configuration

Table 86: CIR Mode with Shaping Rates Greater Than Logical Interface Shaping Rate Hardware Behavior

Table 87: CIR Mode with Excess Rate Configuration

Table 88: CIR Mode with Excess Rate Hardware Behavior

Table 89: Oversubscribed PIR Mode with Transmit Rate Configuration

Table 90: Oversubscribed PIR Mode with Transmit Rate Hardware Behavior

Table 91: Oversubscribed PIR Mode with Transmit Rate and Excess Rate Configuration

Table 92: Oversubscribed PIR Mode with Transmit Rate and Excess Rate Hardware Behavior

Table 93: CIR Mode with Transmit Rate and Excess Rate Configuration

Table 94: CIR Mode with Transmit Rate and Excess Rate Hardware Behavior

Table 95: Excess Priority Configuration

Table 96: Shaper Accuracy of 1-Gbps Ethernet at the Logical Interface Level

Table 97: Shaper Accuracy of 10-Gbps Ethernet at the Logical Interface Level

Table 98: Shaper Accuracy of 1-Gbps Ethernet at the Interface Set Level

Table 99: Shaper Accuracy of 10-Gbps Ethernet at the Interface Set Level

Table 100: Shaper Accuracy of 1-Gbps Ethernet at the Physical Port Level

Table 101: Shaper Accuracy of 10-Gbps Ethernet at the Physical Port Level

Table 102: Port Groups on 10-port 10-Gigabit OSE PIC

Table 103: IQ2 PIC and Enhanced Queuing DPC Compared

Table 104: Junos Priorities Mapped to Enhanced Queuing DPC Hardware Priorities

Table 105: Shaping Rates and WFQ Weights

Table 106: Example Shaping Rates and WFQ Weights

Table 107: Rounding Configured Weights to Hardware Weights

Table 108: Allocating Weights with PIR and CIR on Logical Interfaces

Table 109: Sharing Bandwidth Among Logical Interfaces

Table 110: First Example of Bandwidth Sharing

Table 111: Second Example of Bandwidth Sharing

Table 112: Final Example of Bandwidth Sharing

Table 113: Dedicated Queues for Trio MPC/MIC Interfaces

Table 114: Applying Traffic Control Profiles

Table 115: LSR Default Classification