List of Tables

Table 1: Notice Icons
Table 2: Text and Syntax Conventions
Table 3: Encapsulation Support by Interface Type
Table 4: FPC Numbering for T640 Routers in a Routing Matrix
Table 5: One-to-One FPC Numbering for T640 Routers in a Routing Matrix
Table 6: FPC Numbering for T1600 Routers in a Routing Matrix
Table 7: One-to-One FPC Numbering for T1600 Routers in a Routing Matrix
Table 8: Statements for Physical Interface Properties
Table 9: Media MTU Sizes by Interface Type for M5, M7i with CFEB, M10, M10i with CFEB, M20, and M40 Routers
Table 10: Media MTU Sizes by Interface Type for M40e Routers
Table 11: Media MTU Sizes by Interface Type for M160 Routers
Table 12: Media MTU Sizes by Interface Type for M7i with CFEB-E, M10i with CFEB-E, M320 and M120 Routers
Table 13: Media MTU Sizes by Interface Type for MX Series Routers
Table 14: Media MTU Sizes by Interface Type for T320 Routers
Table 15: Media MTU Sizes by Interface Type for T640 Platforms
Table 16: Media MTU Sizes by Interface Type for J2300 Platforms
Table 17: Media MTU Sizes by Interface Type for J4300 and J6300 Platforms
Table 18: Media MTU Sizes by Interface Type for J4350 and J6350 Platforms
Table 19: Encapsulation Overhead by Encapsulation Type
Table 20: Type 1 PIC Mode Combinations
Table 21: Type 2 PIC Mode Combinations
Table 22: Loopback Modes by Interface Type
Table 23: BERT Capabilities by Interface Type
Table 24: Statements for Logical Interface Properties
Table 25: Signal Handling by Serial Interface Type
Table 26: ATM1 and ATM2 IQ Supported Features
Table 27: ILMI Support by Encapsulation Type
Table 28: Shaping Rate Range by Interface Type
Table 29: ATM1 Traffic-Shaping Rates
Table 30: EPD Threshold Range by Interface Type
Table 31: ATM Logical Interface Encapsulation Types
Table 32: ATM-over-ADSL Operational Modes
Table 33: ATM-over-ADSL Encapsulation Types
Table 34: PIC Support for Enhanced Frame Relay Encapsulation Types
Table 35: Frame Relay DLCI Limitations for Channelized Interfaces
Table 36: Per Unit Scheduler DLCI Limitations for Channelized Interfaces
Table 37: Protocol Family Combinations
Table 38: Clocking Capabilities by Channelized PIC Type
Table 39: Structural Differences: Channelized IQE PICs
Table 40: Structural Differences: Channelized IQ PICs
Table 41: Structural Differences: Channelized PICs
Table 42: OC12-to-DS3 Numbering Scheme
Table 43: Channelized STM1-to-E1 Channel Mapping
Table 44: Channelized STM1-to-T1 Channel Mapping
Table 45: Ranges for Channelized DS3-to-DS0 Configuration
Table 46: Ranges for Channelized T1 IQ Configuration
Table 47: Ranges for Channelized E1 Configuration
Table 48: IMA Frame Synchronization Link State Transition Variables
Table 49: IMA Group Alarms with IMA Standard Requirement Numbers
Table 50: IMA Group Defects with IMA Standard Requirement Numbers
Table 51: IMA Link Alarms with IMA Standard Requirement Numbers
Table 52: IMA Link Defects with IMA Standard Requirement Numbers
Table 53: IMA Link Statistics with IMA Standard Requirement Numbers
Table 54: Subrate Values for E3 Digital Link Compatibility Mode
Table 55: Subrate Values for T3 Digital Link Compatibility Mode
Table 56: VLAN ID Range by Interface Type
Table 57: Configuration Statements Used to Bind VLAN IDs to Logical Interfaces
Table 58: Configuration Statements Used to Associate VLAN IDs to VLAN Demux Interfaces
Table 59: Encapsulation Inside Circuits CCC-Connected by VLAN-Bundled Logical Interfaces
Table 60: Untagged Aggregated Ethernet and LACP Support by PIC and Platform
Table 61: Rewrite Operations on Untagged, Single-Tagged, and Dual-Tagged Frames
Table 62: Applying Rewrite Operations to VLAN Maps
Table 63: Rewrite Operations and Statement Usage for Input VLAN Maps
Table 64: Rewrite Operations and Statement Usage for Output VLAN Maps
Table 65: Input VLAN Map Statements Allowed for ethernet-ccc and ethernet-vpls Encapsulations
Table 66: Output VLAN Map Statements Allowed for ethernet-ccc and ethernet-vpls Encapsulations
Table 67: Rules for Applying Rewrite Operations to VLAN Maps
Table 68: Lowest Priority Defect Options
Table 69: Format of TLVs
Table 70: Type Field Values for Various TLVs for CFM PDUs
Table 71: Port Status TLV Format
Table 72: Port Status TLV Values
Table 73: Interface Status TLV Format
Table 74: Interface Status TLV Values
Table 75: ETH-DM Statistics
Table 76: ETH-DM Frame Counts
Table 77: Capabilities of Gigabit Ethernet IQ and Gigabit Ethernet with SFPs
Table 78: Default Forwarding Classes
Table 79: Mode and Autonegotiation Status (Local)
Table 80: Mode and Autonegotiation Status (Remote)
Table 81: Capabilities of 10-Port 10-Gigabit OSE PICs
Table 82: Handling Oversubscription on 10-ort 10-Gigabit OSE PICs
Table 83: Wavelength-to-Frequency Conversion Matrix
Table 84: PPPoE Trace Operation Flags
Table 85: Type 1 PIC Mode Combinations
Table 86: Type 2 PIC Mode Combinations
Table 87: SONET/SDH Framing Bytes for Specific Speeds
Table 88: SONET/SDH Default Settings
Table 89: SONET/SDH and ATM Active Alarms and Defects