List of Figures

Figure 1: APS Interface
Figure 2: Container Interface
Figure 3: Routing Matrix
Figure 4: Routing Matrix Based on a TX Matrix Plus Router
Figure 5: Interface Slot, PIC, and Port Locations
Figure 6: Clock Sources
Figure 7: Hierarchical Policer
Figure 8: Unicast RPF with Routing Asymmetry
Figure 9: Prefix Accounting with Source and Destination Classes
Figure 10: Layer 2 Switching Circuit Cross-Connect
Figure 11: Example Topology of a Switching Circuit Cross-Connect with Frame Relay CCC Encapsulation
Figure 12: Layer 2.5 Switching Translational Cross-Connect
Figure 13: Interface-to-Interface Circuit Cross-Connect over Aggregated Ethernet Interfaces
Figure 14: Remote Interface-LSP-Interface Circuit Cross-Connect over Aggregated Ethernet Interfaces
Figure 15: ATM-to-Ethernet Interworking
Figure 16: Serial Interface Clocking Mode
Figure 17: Serial Interface LIU Loopback
Figure 18: Serial Interface Local Loopback
Figure 19: Layer 2 Circuit Trunk Topology
Figure 20: Example Topology for Router with Eight Queues
Figure 21: Channelized OC48/STM16 IQE PIC (in SONET Mode)
Figure 22: Channelized OC48/STM16 IQE PIC (in SDH Mode)
Figure 23: Channelized OC12 IQ PIC and Channelized OC12/STM4 IQE PIC (in SONET Mode)
Figure 24: Channelized OC12/STM4 IQE PIC (in SDH Mode)
Figure 25: Channelized OC12/STM4 IQ PIC (in SDH Mode)
Figure 26: Channelized OC3 Ports (in SONET Mode) on Channelized OC3 IQ and Channelized OC3/STM1 IQE PICs
Figure 27: Channelized CSTM1 Ports (in SDH Mode) on Channelized OC3/STM1 IQE PIC
Figure 28: Channelized STM1 IQ PIC
Figure 29: Channelized CDS3/E3 IQE PIC (in DS3 Mode)
Figure 30: Channelized CDS3/E3 IQE PIC (in E3 Mode)
Figure 31: Channelized DS3 IQ PIC
Figure 32: Channelized T1 IQ and IQE PIC
Figure 33: Channelized E1 IQ and IQE PIC
Figure 34: Sample Channelization of OC48/STM16 IQE PIC (SONET Mode)
Figure 35: Sample Channelization of OC48/STM16 IQE PIC (SDH Mode)
Figure 36: Sample Channelization of OC48/STM16 IQE PIC to E3 Channels
Figure 37: T1 Interfaces on a Channelized OC48 PIC
Figure 38: Sample Channelization of OC48 IQE PIC
Figure 39: Sample Channelization of OC12/STM4 IQ or IQE PIC (SONET Mode)
Figure 40: Sample Channelization of OC12/STM4 IQE PIC (SDH Mode)
Figure 41: Sample Channelization of OC12/STM4 IQ PIC (SDH Mode)
Figure 42: Sample Channelization of OC12 PIC (non IQ and IQE)
Figure 43: T1 Interfaces on a Channelized OC12 PIC
Figure 44: Sample Channelization of OC12 IQE PIC
Figure 45: Channelized OC3 IQ Interface Example for Show Interfaces Controller
Figure 46: T1 Interfaces on a Channelized OC3 PIC
Figure 47: Sample Channelization of OC3 IQ or IQE PIC
Figure 48: Sample Channelization of DS3 IQ or IQE PIC
Figure 49: Mobile Backhaul Application
Figure 50: 12-Port T1/E1 Circuit Emulation PIC Possible Interfaces (T1 Size)
Figure 51: 12-Port T1/E1 Circuit Emulation PIC Possible Interfaces (E1 Size)
Figure 52: 4-Port Channelized COC3/STM1 Circuit Emulation PIC Possible Interfaces (T1 Size)
Figure 53: 4-Port Channelized COC3/STM1 Circuit Emulation PIC Possible Interfaces (E1 Size)
Figure 54: Remote and Local E1 Loopback
Figure 55: Remote and Local E3 Loopback
Figure 56: Remote and Local T1 Loopback
Figure 57: Remote and Local T3 Loopback
Figure 58: Symmetric Load Balancing on an 802.3ad LAG on MX Series Routers
Figure 59: Topology of Layer 2.5 Translational Cross-Connect
Figure 60: Edge Device Case for Unrestricted Proxy ARP
Figure 61: Core Device Case for Unrestricted Proxy ARP
Figure 62: Relationship Among MEPs, MIPs, and Maintenance Domain Levels
Figure 63: Relationship Among Bridges, Maintenance Domains, Maintenance Associations, and MEPs
Figure 64: Scope of the E-LMI Protocol
Figure 65: E-LMI Configuration for a Point-to-Point EVC (SVLAN) Monitored by CFM
Figure 66: Layer 2 VPN Topology
Figure 67: Relationship of MEPs, MIPs, and Maintenance Domain Levels
Figure 68: PPPoE Session on an Ethernet Loop
Figure 69: Protocol Packets from the Network to the Router
Figure 70: Protocol Packets from the Router to the Network
Figure 71: Example of a Three-Node Ring Topology
Figure 72: ISDN Backup Topology
Figure 73: Dialer Filter Topology
Figure 74: Bandwidth-on-Demand Topology
Figure 75: Dialer Watch Topology
Figure 76: APS/MSP Configuration Topologies
Figure 77: APS Load Sharing Between Circuit Pairs