The transparent encoding feature provides a phase-correction FIFO buffer. This FIFO buffer aligns the clock and data phase relationship on a transparent encoded circuit in which the clock travels in one direction through the network, and the data travels in the opposite direction. The transparent FIFO buffer is needed because of the latency of signal transport over the IP network.
Figure 1 shows the phase-correction FIFO buffers. You can enable the phase-correction FIFO buffer at either end of the circuit. You would not enable the FIFO buffer at both ends of the circuit.
Figure 1: Transparent Encoding with Phase-Correction FIFO Buffers
Figure 2 shows the paths of the clock and data through the phase-correction FIFO buffer that is enabled on the transparent circuit on the right.
Figure 2: Clock and Data Paths with Transparent Phase-Correction FIFO Buffers