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# Configuring Custom Clocking for CTP Bundles (CTP Menu)

The custom clocking configuration allows you to configure the source for all clocks and specify which clocks are used to sample and transmit data. The configuration provides complete control over how clocks are used, and we recommend that you have a good understanding of circuit and system clocking before you use this configuration.

You can use custom clocking to:

- Configure the interface to use nonstandard clock configurations that meet the timing needs of your application.
- Configure asymmetric clocks.
- Create special configurations for devices such as tactical radios.

Before you begin:

- Disable the bundle before you modify the bundle options.

To configure custom clocking for CTP bundles using the CTP Menu:

1. From the Main Menu, select 1) Bundle Operations.
2. Select 1) CTP.
3. Select a bundle from the list.

   If you select an active bundle, you are prompted to disable the bundle before configuring it.

4. Select 3) Port Config.
5. Select 3) Clock Config.
6. Select 1) Port Clock Config.
7. Select Custom.
8. Configure the options as described in Table 1.

Field | Function | Your Action
--- | --- | ---
DDS Synthesizer Source | Specifies the clock source for the DDS. | Select: User (OI)—Clock is recovered from the user equipment. Adaptive—DDS uses adaptive clocking to recover the clock signal from the remote CTP device. Autobaud—Use for the autobaud feature. This setting enables the monitoring of OAM packets for the other end terminal timing (TT) frequency, and processing to accommodate frequency changes that are detected.
DIV (clk divider) Source | Specifies the source for the divider clock. The DIV clock is an alternate clock generator for the bundle, and its output clock is an even integer divider of its source clock. The divider is used to configure asymmetric circuits. For example, if the source clock is 512 KHz, the output of the DIV clock can be 256 KHz, 128 KHz, 85.333 KHz, etc. | Select: DDS Output—Direct digital synthesizer clock generator. Oscillator—Oscillator system clock.
DIV (clk divider) Value | Specifies the divider clock value. The clock value of the DIV source is divided by this value to obtain the output clock value of the DIV clock. | Enter an even number from 2 through 64,000.
ST (net bound i/f) clk sel | Specifies the clock used for Send Timing on the network bound interface. | Select one (the values that appear depend on whether the bundle is configured as the DCE or as the DTE): OFF—No clock is used.Correct? ST (ext clk)—Send timing clock. The interface clock signal from the DCE to the DTE (CTP device). DDS (synth)—Direct digital synthesizer clock TT (ext clk)—Transmit timing clock. The interface clock signal from the DTE to the DCE (CTP device). RT (ext clk)—Receive timing clock. Interface clock signal from the DCE to the DTE (CTP device). DIV (synth)—Divider clock generator.
RF (net bound fifo) clk sel | Specifies the clock used for Receive Frequency on the network bound interface. | Select one (the values that appear depend on whether the bundle is configured as the DCE or as the DTE): OFF—No clock is used. ST (ext clk)—Send timing clock. The interface clock signal from the DCE to the DTE (CTP device). DDS (synth)—Direct digital synthesizer clock TT (ext clk)—Transmit timing clock. The interface clock signal from the DTE to the DCE (CTP device). RT (ext clk)—Receive timing clock. Interface clock signal from the DCE to the DTE (CTP device). DIV (synth)—Divider clock generator.
RX (net bound scc) clk sel | Specifies the clock used for the Receive Data path on the network bound serial communications controller (SCC). | Select one (the values that appear depend on whether the bundle is configured as the DCE or as the DTE): OFF—No clock is used. ST (ext clk)—Send timing clock. The interface clock signal from the DCE to the DTE (CTP device). DDS (synth)—Direct digital synthesizer clock TT (ext clk)—Transmit timing clock. The interface clock signal from the DTE to the DCE (CTP device). RT (ext clk)—Receive timing clock. Interface clock signal from the DCE to the DTE (CTP device). DIV (synth)—Divider clock generator.
RT (i/f bound i/f) clk sel | Specifies the clock used for Receive Timing on the interface bound interface. This parameter appears only if you have configured the bundle as the DCE. | Select one: OFF—No clock is used. DDS (synth)—Direct digital synthesizer clock TT (ext clk)—Transmit timing clock. The interface clock signal from the DTE to the DCE (CTP device). DIV (synth)—Divider clock generator.
TT (i/f bound i/f) clk sel | Specifies the Transmit Timing clock on the interface bound interface. This parameter appears only if you have configured the bundle as the DTE. | Select one: ST (ext clk)—Send timing clock. The interface clock signal from the DCE to the DTE (CTP device). DDS (synth)—Direct digital synthesizer clock RT (ext clk)—Receive timing clock. Interface clock signal from the DCE to the DTE (CTP device). DIV (synth)—Divider clock generator.
TX (i/f bound scc) clk sel | Specifies the clock used for the Transmit Data path on the interface bound serial communications controller (SCC). | Select one (the values that appear depend on whether the bundle is configured as the DCE or as the DTE): OFF—No clock is used. ST (ext clk)—Send timing clock. The interface clock signal from the DCE to the DTE (CTP device). DDS (synth)—Direct digital synthesizer clock TT (ext clk)—Transmit timing clock. The interface clock signal from the DTE to the DCE (CTP device). RT (ext clk)—Receive timing clock. Interface clock signal from the DCE to the DTE (CTP device). DIV (synth)—Divider clock generator.

#### Published: 2011-01-09

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