Log in
|
How to Buy
|
Contact Us
|
United States (Change)

## Choose Country

### North America

- United States

### Europe

- Deutschland - Germany
- España - Spain
- France
- Italia - Italy
- Россия - Russia
- United Kingdom

### Asia Pacific

- Asean Region (Vietnam, Indonesia, Singapore, Malaysia)
- Australia
- 中国 - China
- India
- 日本 - Japan
- 대한민국 - Korea
- 台灣 - Taiwan

Remember my choice

# Technical Documentation

Download Software
Research a Problem
Case Management
Contract & Product Management
Technical Documentation
Documentation Archive
Report Documentation Bug
Enterprise MIBs
File Format Help
Glossary
Portable Libraries
End-of-Life Products
Contact Support
Guidelines and Policies
Security Resources
Feedback

## Documentation Search

Advanced Search | Search Tips

## Related Documentation

- Transparent Encoding Applications and Support Overview
- How Basic Transparent Encoding Works
- Using Phase-Correction FIFO Buffer with Transparent Encoding
- Using Send Timing (ST) Clocking for Higher Speed Circuits with Transparent Encoding

# Configuring Transparent Encoding for CTP Bundles (CTP Menu)

This topic describes how to configure transparent encoding for CTP bundles. You must configure transparent encoding on each end of the circuit.

To reduce transport latency, we recommend that you use the smallest buffer values possible for networks.

Before you begin:

- Disable the bundle before you modify the bundle options.

To configure transparent encoding using the CTP Menu:

1. From the Main Menu, select 1) Bundle Operations.
2. Select 1) CTP.
3. Select a bundle from the list.

   If you select an active bundle, you are prompted to disable the bundle before configuring it.

4. Select 3) Port Config.
5. Select 2) Interface.
6. Set Mode to DCE and set Encoding to TRANS.
7. Follow the onscreen instructions to configure the options as described in Table 1.

Field | Function | Your Action
--- | --- | ---
Enter Synthesized port rate (KHz) | Specifies the speed of the port. For transparent mode circuits, the port speed is the sample rate for user data. Therefore, the port rate should be a multiple of the user data rate. In networks without bandwidth constraints, we recommend a multiple of 10. | Enter a number from 0.00100 through 1024.000000 KHz.
Enable adaptive clocking? | Specifies whether adaptive clocking is enabled for this circuit. If both end nodes are not locked to a clock reference, we recommend that you enable one end (not both) for adaptive clocking | Specify y (yes) or n (no).
Initialize adaptive clocking parameters? y[n]: y | If you enabled adaptive clocking, specifies whether or not to initialize adaptive clocking parameters to their default values, which depend on port speed, packet size, and buffering parameters set on the bundle. We recommend the following settings: If you are configuring the bundle for adaptive clocking for the first time, enter y. If you have previously configured the bundle to optimize adaptive clocking for this network, enter n. | Specify y (yes) or n (no).
Enable 16 bit FIFO? | Enables or disables the phase-correction FIFO buffer. This FIFO buffer aligns the clock and data phase relationship on a TRANS encoded circuit in which the clock travels in one direction and the data travels in the opposite direction. Enable this FIFO buffer at one end of the circuit, but not at both ends. | Specify y (yes) or n (no).
Invert FIFO Write clock? | Appears only if you enable the 16-Bit Jitter Absorption FIFO buffer. Specifies whether or not to invert the FIFO write clock. | Specify y (yes) or n (no).
Invert FIFO Read clock? | Appears only if you enable the 16-Bit Jitter Absorption FIFO buffer. Specifies whether or not to invert the FIFO read clock. | Specify y (yes) or n (no).
Use ST lead (instead of RTS/CTS)? | Specifies that the circuit uses the ST lead instead of the RTS and CTS leads to sample local SD/TT/RTS/DTR signals and forward them to the remote RD/RT/CTS/DSR signals. The RTS and DTR leads are subject to additional delay and jitter because they are signaling leads. On higher-speed circuits, the delay and jitter on these paths make the signal choices nonoptimal. Therefore, you can specify that the circuit uses the ST lead instead of the RTS and CTS leads, which will not have this delay and jitter. | Specify y (yes) or n (no).
Is ST an input? | If you specify that the circuit uses the ST lead instead of the RTS and CTS leads, you can specify if the ST lead is an input lead. | Specify y (yes) or n (no)

## Related Documentation

- Transparent Encoding Applications and Support Overview
- How Basic Transparent Encoding Works
- Using Phase-Correction FIFO Buffer with Transparent Encoding
- Using Send Timing (ST) Clocking for Higher Speed Circuits with Transparent Encoding

#### Published: 2011-01-09

﻿
Site Map / RSS Feeds / Careers / Accessibility / Feedback / Privacy & Policy / Legal Notices
Copyright© 1999-2011 Juniper Networks, Inc. All rights reserved.
Help
|
My Account
|
Log Out