This topic describes how to configure transparent encoding for CTP bundles. You must configure transparent encoding on each end of the circuit.
To reduce transport latency, we recommend that you use the smallest buffer values possible for networks.
Before you begin:
To configure transparent encoding parameters for CTP bundles using CTPView:
Table 1: CTP Bundle Transparent Encoding Parameter Settings in CTPView
Field | Function | Your Action |
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Port Speed | Specifies the sample rate for user data. The port rate should be a multiple of the user data rate. | Enter a number from 0.00100 through 12288.00000 kHz. |
Clock Cfg | Specifies the clocking method used for the transparent circuit. To prevent errors in transport, both ends of a circuit must be synchronized with each other. You can accomplish this by either locking each end of the circuit to a common reference or by enabling adaptive clocking at one end of a circuit. | Select one:
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16-Bit Jitter Absorption FIFO | Enables or disables the phase correction FIFO buffer. This FIFO buffer aligns the clock and data phase relationship on a TRANS encoded circuit in which the clock travels in one direction and the data travels in the opposite direction. Enable this FIFO buffer at one end of the circuit, but not at both ends. | Select one:
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Invert FIFO Write Clock | Appears only if you enable the 16-Bit Jitter Absorption FIFO buffer. Specifies whether or not to invert the FIFO buffer write clock. | Select one:
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Invert FIFO Read Clock | Appears only if you enable the 16-Bit Jitter Absorption FIFO buffer. Specifies whether or not to invert the FIFO read clock. | Select one:
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Use ST Lead (instead of RTS/CTS) | Appears only if you enable the 16-Bit Jitter Absorption FIFO buffer . Specifies that the circuit uses the ST lead instead of the RTS and CTS leads to sample local SD/TT/RTS/DTR signals and forward them to the remote RD/RT/CTS/DSR signals. The RTS and DTR signals are subject to additional delay and jitter because they are signaling leads. On higher-speed circuits, the delay and jitter on these paths make the signal choices nonoptimal. Therefore, you can specify that the circuit uses the ST lead instead of the RTS and CTS leads, which will not have this delay and jitter. | Select one:
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