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## Related Documentation

- Transparent Encoding Applications and Support Overview
- How Basic Transparent Encoding Works
- Using Phase-Correction FIFO Buffer with Transparent Encoding
- Using Send Timing (ST) Clocking for Higher Speed Circuits with Transparent Encoding

# Configuring Transparent Encoding for CTP Bundles (CTPView)

This topic describes how to configure transparent encoding for CTP bundles. You must configure transparent encoding on each end of the circuit.

To reduce transport latency, we recommend that you use the smallest buffer values possible for networks.

Before you begin:

- Log in to the CTPView software at least at the Net_Admin level.
- Connect the CTPView server to the CTP device for which you want to configure bundles.
- Disable the bundle before you modify the bundle options.

To configure transparent encoding parameters for CTP bundles using CTPView:

1. In the side pane, select Bundle > Configuration.
2. Run your mouse over the Display and Select an Existing Bundle bar.
3. In the table of bundles, select the bundle that you want to modify.
4. Under Port Options, set Serial Encoding to TRANS.
5. Configure the Port Speed and Clock Cfg and described in Table 1.
6. Under Port Options, place a check mark in the Advanced Options Show check box to display advanced parameters, and configure the parameters described in Table 1.
7. Click Click to Submit Bundle AND Port Changes.

Table 1: CTP Bundle Transparent Encoding Parameter Settings in CTPView

Field | Function | Your Action
--- | --- | ---
Port Speed | Specifies the sample rate for user data. The port rate should be a multiple of the user data rate. | Enter a number from 0.00100 through 12288.00000 kHz.
Clock Cfg | Specifies the clocking method used for the transparent circuit. To prevent errors in transport, both ends of a circuit must be synchronized with each other. You can accomplish this by either locking each end of the circuit to a common reference or by enabling adaptive clocking at one end of a circuit. | Select one: TRANS - Master End—This end of the circuit generates a clock signal and sends it to the remote end. Configure TRANS - Slave End at the remote end. TRANS - Slave End—This end of the circuit uses adaptive clocking to receive the clock signal from the remote end. The clock slave uses its period to determine when to sample data and how to transmit data across the link. If you specify slave end, the adaptive clocking configuration appears. See Configuring Adaptive Clocking for CTP Bundles (CTPView). Custom—The custom clocking configuration is used. See Configuring Custom Clocking for CTP Bundles (CTPView).
16-Bit Jitter Absorption FIFO | Enables or disables the phase correction FIFO buffer. This FIFO buffer aligns the clock and data phase relationship on a TRANS encoded circuit in which the clock travels in one direction and the data travels in the opposite direction. Enable this FIFO buffer at one end of the circuit, but not at both ends. | Select one: DISABLED ENABLED
Invert FIFO Write Clock | Appears only if you enable the 16-Bit Jitter Absorption FIFO buffer. Specifies whether or not to invert the FIFO buffer write clock. | Select one: DISABLED ENABLED
Invert FIFO Read Clock | Appears only if you enable the 16-Bit Jitter Absorption FIFO buffer. Specifies whether or not to invert the FIFO read clock. | Select one: DISABLED ENABLED
Use ST Lead (instead of RTS/CTS) | Appears only if you enable the 16-Bit Jitter Absorption FIFO buffer . Specifies that the circuit uses the ST lead instead of the RTS and CTS leads to sample local SD/TT/RTS/DTR signals and forward them to the remote RD/RT/CTS/DSR signals. The RTS and DTR signals are subject to additional delay and jitter because they are signaling leads. On higher-speed circuits, the delay and jitter on these paths make the signal choices nonoptimal. Therefore, you can specify that the circuit uses the ST lead instead of the RTS and CTS leads, which will not have this delay and jitter. | Select one: DISABLED INPUT—Enables the ST lead and specifies that the ST lead is an input lead. OUTPUT—Enables the ST lead and specifies that the ST lead is an output lead.

## Related Documentation

- Transparent Encoding Applications and Support Overview
- How Basic Transparent Encoding Works
- Using Phase-Correction FIFO Buffer with Transparent Encoding
- Using Send Timing (ST) Clocking for Higher Speed Circuits with Transparent Encoding

#### Published: 2011-01-09

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