Configuring Custom Clocking for CTP Bundles (CTPView)
The custom clocking configuration allows you to configure the source for all clocks and specify which clocks are used to sample and transmit data. The configuration provides complete control over how clocks are used, and we recommend that you have a good understanding of circuit and system clocking before you use this configuration.
You can use custom clocking to:
- Configure the interface to use nonstandard clock configurations that meet the timing needs of your application.
- Configure asymmetric clocks.
- Create special configurations for devices such as tactical radios.
Before you begin:
- Log in to the CTPView software at least at the Net_Admin level.
- Connect the CTPView server to the CTP device for which you want to configure bundles.
- Disable the bundle before you modify the bundle options.
To configure custom clocking for CTP bundles using CTPView:
- In the side pane, select Bundle > Configuration.
- Run your mouse over the Display and Select an Existing Bundle bar.
- In the table of bundles, select the bundle that you want to modify.
- Under Port Options in the Clock Cfg field, select Custom.
- Place a check mark in the Custom Clocking
Options show check box to display custom clocking parameters,
and configure the parameters described in Table 1.
The options vary depending on the I/F Type selected.
- Click Click to Submit Bundle AND Port Changes.
Table 1: CTP Bundle Custom Clocking Settings in CTPView
| Field | Function | Your Action |
|---|---|---|
DDS Frequency | Specifies a fixed frequency for the Direct Digital Synthesizer (DDS). | |
DDS Post Divider | Programmable divider that divides a clock by an even number. | Enter a number from 0 through 4. |
DDS Source | Specifies the clock source for the DDS. | Select one:
|
DIV Source | Specifies the source for the divider clock. The DIV clock is an alternate clock generator for the bundle, and its output clock is an even integer divider of its source clock. The divider is used to configure asymmetric circuits. For example, if the source clock is 512 KHz, the output of the DIV clock can be 256 KHz, 128 KHz, 85.333 KHz, etc. | Select one:
|
DIV Clk Divider | Specifies the divider clock value. The clock value of the DIV source is divided by this value to obtain the output clock value of the DIV clock. | Enter an even number from 2 through 64,000. |
ST Net Bound I/F Clock | Specifies the clock used for Send Timing on the network bound interface. | Select one:
|
RF Net Bound I/F Clock | Specifies the clock used for Receive Frequency on the network bound interface. | Select one:
|
RX Net Bound SCC Clock | Specifies the clock used for the Receive Data path on the network bound serial communications controller (SCC). | Select one:
|
RT I/F Bound I/F Clock | Specifies the clock used for Receive Timing on the interface bound interface. | Select one:
|
TX I/F Bound SCC Clock | Specifies the clock used for the Transmit Data path on the interface bound serial communications controller (SCC). | Select one:
|
