List of Tables

Table 1: Notice Icons

Table 2: Text and Syntax Conventions

Table 3: Technical Documentation for Supported Routing Platforms

Table 4: JUNOS Software Network Operations Guides

Table 5: JUNOS Software for J-series Services Routers and SRX-series Services Gateways Documentation

Table 6: Additional Books Available Through http://www.juniper.net/books

Table 7: Encapsulation Support by Interface Type

Table 8: FPC Numbering for T640 Routing Nodes in a Routing Matrix

Table 9: One-to-One FPC Numbering for T640 Routing Nodes in a Routing Matrix

Table 10: Statements for Physical Interface Properties

Table 11: Media MTU Sizes by Interface Type for M5, M7i, M10, M10i, M20, and M40 Routers

Table 12: Media MTU Sizes by Interface Type for M40e Routers

Table 13: Media MTU Sizes by Interface Type for M160 Routers

Table 14: Media MTU Sizes by Interface Type for M320 and M120 Platforms

Table 15: Media MTU Sizes by Interface Type for T320 Platforms

Table 16: Media MTU Sizes by Interface Type for T640 Platforms

Table 17: Media MTU Sizes by Interface Type for J2300 Platforms

Table 18: Media MTU Sizes by Interface Type for J4300 and J6300 Platforms

Table 19: Media MTU Sizes by Interface Type for J4350 and J6350 Platforms

Table 20: Encapsulation Overhead by Encapsulation Type

Table 21: Type 1 PIC Mode Combinations

Table 22: Type 2 PIC Mode Combinations

Table 23: Loopback Modes by Interface Type

Table 24: BERT Capabilities by Interface Type

Table 25: Statements for Logical Interface Properties

Table 26: Signal Handling by Serial Interface Type

Table 27: ATM1 and ATM2 IQ Supported Features

Table 28: ILMI Support by Encapsulation Type

Table 29: Shaping Rate Range by Interface Type

Table 30: ATM1 Traffic-Shaping Rates

Table 31: EPD Threshold Range by Interface Type

Table 32: ATM Logical Interface Encapsulation Types

Table 33: ATM-over-ADSL Operational Modes

Table 34: ATM-over-ADSL Encapsulation Types

Table 35: PIC Support for Enhanced Frame Relay Encapsulation Types

Table 36: Frame Relay DLCI Limitations for Channelized Interfaces

Table 37: Per Unit Scheduler DLCI Limitations for Channelized Interfaces

Table 38: Clocking Capabilities by Channelized PIC Type

Table 39: Structural Differences: Channelized PICs, Channelized IQ PICs, and Channelized IQE PICs

Table 40: Ranges for Channelized E1 Configuration

Table 41: OC12-to-DS3 Numbering Scheme

Table 42: Channelized STM1-to-E1 Channel Mapping

Table 43: Ranges for Channelized T1 IQ Configuration

Table 44: Ranges for Channelized DS3-to-DS0 Configuration

Table 45: Subrate Values for E3 Digital Link Compatibility Mode

Table 46: Subrate Values for T3 Digital Link Compatibility Mode

Table 47: VLAN ID Range by Interface Type

Table 48: Untagged Aggregated Ethernet and LACP Support by PIC and Platform

Table 49: Rewrite Operations on Not Tagged, Single-Tagged, and Dual-Tagged Frames

Table 50: Applying Rewrite Operations to VLAN Maps

Table 51: Rewrite Operations and Statement Usage for Input VLAN Maps

Table 52: Rewrite Operations and Statement Usage for Output VLAN Maps

Table 53: Capabilities of Gigabit Ethernet IQ and Gigabit Ethernet with SFPs

Table 54: Default Forwarding Classes

Table 55: Mode and Autonegotiation Status (Local)

Table 56: Mode and Autonegotiation Status (Remote)

Table 57: Wavelength-to-Frequency Conversion Matrix

Table 58: Type 1 PIC Mode Combinations

Table 59: Type 2 PIC Mode Combinations

Table 60: SONET/SDH Framing Bytes for Specific Speeds

Table 61: SONET/SDH Default Settings

Table 62: SONET/SDH and ATM Active Alarms and Defects

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