List of Figures

Figure 1: APS Interface

Figure 2: Container Interface

Figure 3: Routing Matrix

Figure 4: Interface Slot, PIC, and Port Locations

Figure 5: Clock Sources

Figure 6: DLSw Ethernet Redundancy Topology

Figure 7: Unicast RPF with Routing Asymmetry

Figure 8: Prefix Accounting with Source and Destination Classes

Figure 9: Layer 2 Switching Circuit Cross-Connect

Figure 10: Example Topology of a Switching Circuit Cross-Connect with Frame Relay CCC Encapsulation

Figure 11: Layer 2.5 Switching Translational Cross-Connect

Figure 12: Interface-to-Interface Circuit Cross-Connect over Aggregated Ethernet Interfaces

Figure 13: Remote Interface-LSP-Interface Circuit Cross-Connect over Aggregated Ethernet Interfaces

Figure 14: ATM-to-Ethernet Interworking

Figure 15: Serial Interface Clocking Mode

Figure 16: Serial Interface LIU Loopback

Figure 17: Serial Interface Local Loopback

Figure 18: Layer 2 Circuit Trunk Topology

Figure 19: Example Topology for Router with Eight Queues

Figure 20: Channelized OC48/STM16 IQE PIC (in SONET Mode)

Figure 21: Channelized OC48/STM16 IQE PIC (in SDH Mode)

Figure 22: Channelized OC12 IQ PIC and Channelized OC12/STM4 IQE PIC (in SONET Mode)

Figure 23: Channelized OC12/STM4 IQE PIC (in SDH Mode)

Figure 24: Channelized OC3 Ports (in SONET Mode) on Channelized OC3 IQ and Channelized OC3/STM1 IQE PICs

Figure 25: Channelized CSTM1 Ports (in SDH Mode) on Channelized OC3/STM1 IQE PIC

Figure 26: Channelized STM1 IQ PIC

Figure 27: Channelized CDS3/E3 IQE PIC (in DS3 Mode)

Figure 28: Channelized CDS3/E3 IQE PIC (in E3 Mode)

Figure 29: Channelized DS3 IQ PIC

Figure 30: Channelized E1 IQ PIC

Figure 31: Channelized OC3 IQ Interface Example for Show Interfaces Controller

Figure 32: T1 Interfaces on a Channelized OC3 PIC

Figure 33: Sample Channelization of OC3 IQ or IQE PIC

Figure 34: Sample Channelization of OC12/STM4 IQ or IQE PIC (SONET Mode)

Figure 35: Sample Channelization of OC12/STM4 IQ or IQE PIC (SDH Mode)

Figure 36: Sample Channelization of OC12/STM4 PIC

Figure 37: T1 Interfaces on a Channelized OC12 PIC

Figure 38: Sample Channelization of OC12 IQ or IQE PIC

Figure 39: Sample Channelization of DS3 IQ or IQE PIC

Figure 40: Mobile Backhaul Application

Figure 41: Remote and Local E1 Loopback

Figure 42: Remote and Local E3 Loopback

Figure 43: Remote and Local T1 Loopback

Figure 44: Remote and Local T3 Loopback

Figure 45: Topology of Layer 2.5 Translational Cross-Connect

Figure 46: Edge Device Case for Unrestricted Proxy ARP

Figure 47: Core Device Case for Unrestricted Proxy ARP

Figure 48: Relationship of MEPs, MIPs, and Maintenance Domain Levels

Figure 49: Relationship of Bridges, Maintenance Domains, Maintenance Associations, and MEPs

Figure 50: PPPoE Session on an Ethernet Loop

Figure 51: ISDN Backup Topology

Figure 52: Dialer Filter Topology

Figure 53: Bandwidth-on-Demand Topology

Figure 54: Dialer Watch Topology

Figure 55: APS/MSP Configuration Topologies

Figure 56: APS Load Sharing Between Circuit Pairs

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