Configuring the Serial Clocking Mode

By default, serial interfaces use loop clocking mode. For EIA-530 and V.35 interfaces, you can configure each port on the PIC independently to use loop, DCE, or internal clocking mode. For X.21 interfaces, only loop clocking mode is supported.

The three clocking modes work as follows:

• Loop clocking mode—Uses the DCE’s RX clock to clock data from the DCE to the DTE.
• DCE clocking mode—Uses the TXC clock, which is generated by the DCE specifically to be used by the DTE as the DTE’s transmit clock.
• Internal clocking mode—Also known as line timing, uses an internally generated clock. You can configure the speed of this clock by including the clock-rate statement at the [edit interfaces se-pim/0/port serial-options] or [edit interfaces se-fpc/pic/port dte-options] hierarchy levels. For more information about the DTE clock rate, see Configuring the DTE Clock Rate.

Note that DCE clocking mode and loop clocking mode use external clocks generated by the DCE.

Figure 15 shows the clock sources of loop, DCE, and internal clocking modes.

Figure 15: Serial Interface Clocking Mode

To configure the clocking mode of a serial interface, include the clocking-mode statement:

You can include this statement at the following hierarchy levels:

• [edit interfaces se-pim/0/port serial-options]
• [edit interfaces se-fpc/pic/port serial-options]

For more information about clocking on serial interfaces, see the following sections:

• Serial Interface Clocking Mode
• Inverting the Serial Interface Transmit Clock
• Configuring the DTE Clock Rate

Inverting the Serial Interface Transmit Clock

When an externally timed clocking mode (DCE or loop) is used, long cables might introduce a phase shift of the DTE-transmitted clock and data. At high speeds, this phase shift might cause errors. Inverting the transmit clock corrects the phase shift, thereby reducing error rates.

By default, the transmit clock is not inverted. To invert the transmit clock, include the transmit-clock invert statement:

You can include this statement at the following hierarchy levels:

• [edit interfaces se-pim/0/port serial-options]
• [edit interfaces se-fpc/pic/port serial-options]

Configuring the DTE Clock Rate

By default, the serial interface has a clock rate of 16.384 MHz. For EIA-530 and V.35 interfaces with internal clocking mode configured, you can configure the clock rate. For more information about internal clocking mode, see Configuring the Serial Clocking Mode.

To configure the clock rate, include the clock-rate statement:

You can include this statement at the following hierarchy levels:

• [edit interfaces se-pim/0/port serial-options]
• [edit interfaces se-fpc/pic/port serial-options]

You can configure the following interface speeds:

• 2.048 MHz
• 2.341 MHz
• 2.731 MHz
• 3.277 MHz
• 4.096 MHz
• 5.461 MHz
• 8.192 MHz
• 16.384 MHz

Although the serial interface is intended for use at the default rate of 16.384 MHz, you might need to use a slower rate if any of the following conditions prevail:

• The interconnecting cable is too long for effective operation.
• The interconnecting cable is exposed to an extraneous noise source that might cause an unwanted voltage in excess of +1 volt measured differentially between the signal conductor and circuit common at the load end of the cable, with a 50-ohm resistor substituted for the generator.
• You need to minimize interference with other signals.
• You need to invert signals.

For detailed information about the relationship between signaling rate and interface cable distance, see the following standards:

• EIA-422-A, Electrical Characteristics of Balanced Voltage Digital Interface Circuits
• EIA-423-A, Electrical Characteristics of Unbalanced Voltage Digital Interface Circuits

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