Configuring Channelized OC3 IQ and IQE Interfaces

This chapter describes how to configure interfaces on Channelized OC3 IQ and IQE PICs, as follows:

• Channelized OC3 IQ and IQE Overview
• Partitions, OC Slices, Interface Types, and Time Slots
• Configuring a Clear Channel on Channelized OC3 IQ and IQE PICs
• Configuring T3 IQ Interfaces
• Configuring T1 and NxDS0 Interfaces
• Configuring Fractional T1 IQ Interfaces
• Configuring Link PIC Failover on Channelized OC3 IQ and IQE Interfaces

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