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Note: Channelized intelligent queuing (IQ) and channelized enhanced intelligent queuing (IQE) interfaces require M-series Enhanced Flexible PIC Concentrators (FPCs) and MX-series Enhanced Flexible PIC Concentrators (FPCs). Wherever JUNOS configuration guides refer to channelized interfaces and PICs without the “intelligent queuing IQ or IQE” descriptor, they are referring to the original channelized interfaces and PICs. M40e routers with COC12 IQE or COC48 IQE interfaces have a maximum limitation of 784 physical interfaces per COC12 IQE or COC48 IQE PIC. Channelized 4xCOC12 IQE PICs support deep-channelization of up to six oc-slices (STS1) per port. For example, only 6 oc-slices can be channelized to ct1/t1 or ce1/e1. Channelized COC48 IQE PICs support deep-channelization of up to six oc-slices (STS1) in a block of 12 contiguous oc-slices. For example, only 6 oc-slices out of oc-slice 1-12 can be channelized to ct1/t1 or ce1/e1. The PIC supports deep-channelization of maximum 24 oc-slices in this way. Channelized OC48 IQE PICs do not support STS-48 clear-channel mode. IQ and IQE PICs do not support aggregated SONET (link bonding). For channelized IQ and IQE logical interfaces, you can configure class of service (CoS). For more information, see the JUNOS Class of Service Configuration Guide. |
