Packet Flow on MX-series Platforms

The CoS architecture for MX-series Ethernet services routers such as the MX960 router is similar in concept, but different in particulars, from other routing platforms. The general architecture for the MX-series routing platform is shown in Figure 3.

Figure 3: MX-series Packet Forwarding and Data Flow

Note: In spite of the similarity in designation, the MX-series architecture is different from the M-series routers. However, all Layer 3 JUNOS software CoS functions are supported on the MX-series Ethernet Services routers. In addition, Layer 3 CoS capabilities, with the exception of traffic shaping, are supported on virtual LANs (VLANs) that span multiple ports.

The MX-series routing platform can classify incoming packets at the ingress Dense Port Concentrator (DPC). Fixed classification places all packets in the same forwarding class, or the usual MF or BA classifications can be used to treat packets differently. BA classification with firewall filters can be used for classification based on IP precedence, DSCP, IEEE, or other bits in the frame or packet header.

However, the MX-series routing platforms can also employ multiple BA classifiers on the same logical interface. The logical interfaces do not have to employ the same type of BA classifier. For example, a single logical interface can use classifiers based on IP precedence as well as IEEE 802.1p. If the CoS bits of interest are on the inner VLAN tag of a dual-tagged VLAN interface, the classifier can examine either the inner or outer bits. (By default, the classification is done based on the outer VLAN tag.)

Internal fabric scheduling is based on only two queues: high and low priority. Strict-high priority queuing is also supported in the high-priority category.

Egress port scheduling supports up to eight queues per port using a form of round-robin queue servicing. The supported priority levels are strict-high, high, medium-high, medium-low, and low. The MX-series architecture supports both early discard and tail drop on the queues.

All CoS features are supported at line rate.

The fundamental flow of a packet subjected to CoS is different in the MX-series with integrated chips than it is in the M-series and T-series routers, which have a different packet-handling architecture.

The way that a packet makes its way through an M-series or T-series router with Intelligent Queuing 2 (IQ2) PICs is shown in Figure 4. Note that the per-VLAN scheduling and shaping are done on the PIC whereas all other CoS functions at the port level are performed on the Packet Forwarding Engine.

Figure 4: Packet Handling on the M-series and T-series Routers

The way that a packet makes its way through an MX-series router with Enhanced Queuing DPCs is shown in Figure 5. Note that the scheduling and shaping are done with an integrated architecture on the DPC along with all other CoS functions. In particular, scheduling and shaping are done on the Ethernet services engine network processing unit (ESE NPU). Hierarchical scheduling is supported on the output side only.

Figure 5: Packet Handling on the MX-series Routers

MX-series routers, especially the MX960 Ethernet Services router, have several features that differ from the usual CoS features in the JUNOS software as described in Packet Flow Through the CoS Process.

The MX960 router allows fixed classification of traffic. All packets on a logical interface can be put into the same forwarding class:

As on other platforms, the MX-series routers allow BA classification, the classifying of packets into different forwarding classes (up to eight) based on a value in the packet header. However, MX-series routers allow a mixture of BA classifiers (IEEE 802.1p and others) for logical interfaces on the same port, as shown in the following example:

In this case, the IEEE classifier is applied to Layer 2 traffic and the Internet precedence classifier is applied to Layer 3 (IP) traffic. The IEEE classifier can also perform BA classification based on the bits of either the inner or outer VLAN tag on a dual-tagged logical interface, as shown in the following example:

The default action is based on the outer VLAN tag’s IEEE precedence bits.

As on other platforms, the BA classification can be overridden with a multifield classifier in the action part of a firewall filter. Rewrites are handled as on other platforms, but MX-series routers support classifications and rewrites for aggregated Ethernet (ae-) logical interfaces.

On MX-series routers, the 64 classifier limit is a theoretical upper limit. In practice, you cannot configure 64 classifiers. Three values are used internally by the default IP precedence, IPv6, and EXP classifiers. Two other classifiers are used for forwarding class and queue operations. This leaves 59 classifiers for configuration purposes. If you configure Differentiated Services code point (DSCP) rewrites for MPLS, the maximum number of classifiers you can configure will be less than 59.

On MX-series routers, IEEE 802.1 classifier bit rewrites are determined by forwarding class and packet priority, not by queue number and packet priority as on other platforms.

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