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Hardware Capabilities and Limitations

Juniper Networks J-series, T-series, M320, and other M-series platforms with enhanced Flexible PIC Concentrators (FPCs) have more CoS capabilities than M-series routers that use other FPC models. Table 9 lists the differences. MX-series information is listed in MX-series CoS Hardware Capabilities and Limitations.

To determine whether your M-series routing platform is equipped with an enhanced FPC, issue the show chassis hardware command. The presence of an enhanced FPC is designated by the E-FPC description in the output.

user@host> show chassis hardware

Hardware inventory:
Item              Version  Part number Serial number     Description
Chassis                                31959             M7i
Midplane         REV 02   710-008761   CA0209            M7i Midplane
Power Supply 0   REV 04   740-008537   PD10272           AC Power Supply
Routing Engine   REV 01   740-008846   1000396803        RE-5.0
CFEB             REV 02   750-009492   CA0166            Internet Processor IIv1
FPC 0                                                    E-FPC
  PIC 0          REV 04   750-003163   HJ6416            1x G/E, 1000 BASE-SX
  PIC 1          REV 04   750-003163   HJ6423            1x G/E, 1000 BASE-SX
  PIC 2          REV 04   750-003163   HJ6421            1x G/E, 1000 BASE-SX
  PIC 3          REV 02   750-003163   HJ0425            1x G/E, 1000 BASE-SX
FPC 1                                                    E-FPC
  PIC 2          REV 01   750-009487   HM2275            ASP - Integrated
  PIC 3          REV 01   750-009098   CA0142            2x F/E, 100 BASE-TX

J-series Services Routers do not use FPCs. Instead, they use Physical Interface Modules (PIMs), which are architecturally like FPCs but functionally like Physical Interface Cards (PICs). Both PIMs and PICs provide the interfaces to the routing platforms.

In Table 9, the information in the column titled “M320 and T-series FPCs” is valid for all M320 and T-series FPCs, including Enhanced II FPCs.

Table 9: CoS Hardware Capabilities and Limitations

Feature	J-series PIMs	M-series FPC	M-series Enhanced FPCs	M320 and T-series FPCs	Comments
Classifiers
Maximum number per FPC, PIC, or PIM	64	1	8	64	For M-series FPCs, the one-classifier limit includes the default IP precedence classifier. If you create a new classifier and apply it to an interface, the new classifier does not override the default classifier for other interfaces on the same FPC. In general, the first classifier associated with a logical interface is used. The default classifier can be replaced only when a single interface is associated with the default classifier. For more information, see Table 25.
dscp	Yes	No	Yes	Yes	On all platforms, you cannot configure IP precedence and DiffServ code point (DSCP) classifiers on a single logical interface, because both apply to IPv4 packets. For more information, see Table 25.
dscp-ipv6	Yes	No	Yes	Yes	For T-series platforms, you can apply separate classifiers for IPv4 and IPv6 packets per logical interface. For M-series enhanced FPCs, you cannot apply separate classifiers for IPv4 and IPv6 packets. Classifier assignment works as follows: If you assign a DSCP classifier only, IPv4 and IPv6 packets are classified using the DSCP classifier. If you assign an IP precedence classifier only, IPv4 and IPv6 packets are classified using the IP precedence classifier. The lower three bits of the DSCP field are ignored because IP precedence mapping requires the upper three bits only. If you assign either the DSCP or the IP precedence classifier in conjunction with the DSCP IPv6 classifier, the commit fails. If you assign a DSCP IPv6 classifier only, IPv4 and IPv6 packets are classified using the DSCP IPv6 classifier, but the commit displays a warning message. For more information, see Table 25.
ieee-802.1p	Yes	No	Yes	Yes	On M-series enhanced FPCs and T-series platforms, if you associate an IEEE 802.1p classifier with a logical interface, you cannot associate any other classifier with that logical interface. For more information, see Table 25. For most PICs, if you apply an IEEE 802.1p classifier to a logical interface, you cannot apply non-IEEE classifiers on other logical interfaces on the same physical interface. This restriction does not apply to Gigabit Ethernet IQ2 PICs.
inet-precedence	Yes	Yes	Yes	Yes	On all platforms, you cannot assign IP precedence and DSCP classifiers to a single logical interface, because both apply to IPv4 packets. For more information, see Table 25.
mpls-exp	Yes	Yes	Yes	Yes	For M-series FPCs, only the default MPLS EXP classifier is supported; the default MPLS EXP classifier takes the EXP bits 1 and 2 as the output queue number.
Loss priorities based on the Frame Relay discard eligible (DE) bit	Yes	No	No	No	–
Drop Profiles
Maximum number per FPC, PIC, or PIM	32	2	16	32	–
Per queue	Yes	No	Yes	Yes	–
Per loss priority	Yes	Yes	Yes	Yes	–
Per Transmission Control Protocol (TCP) bit	Yes	No	Yes	Yes	–
Policing
Adaptive shaping for Frame Relay traffic	Yes	No	No	No	–
Traffic policing	Yes	Yes	Yes	Yes	–
Two-rate tricolor marking (TCM)	No	No	No	Yes	Allows you to configure up to four loss priorities. Two-rate TCM is supported on T-series platforms with Enhanced II FPCs and the T640 platform with Enhanced Scaling FPC4. For more information, see Configuring Tricolor Marking Policers.
Virtual channels	Yes	No	No	No	–
Queuing					Gigabit Ethernet IQ2 PICs support only one queue in the scheduler map with medium-high, high, or strict-high priority. If more than one queue is configured with high or strict-high priority, the one that appears first in the configuration is implemented as strict-high priority. This queue receives unlimited transmission bandwidth. The remaining queues are implemented as low priority, which means they might be starved. On the IQE PIC, you can rate-limit the strict-high and high queues. Without this limiting, traffic that requires low latency (delay) such as voice can block the transmission of medium-priority and low-priority packets. Unless limited, high and strict-high traffic will always be sent before lower priority traffic.
Priority	Yes	No	Yes	Yes	Support for the medium-low and medium-high queuing priority mappings varies by FPC type. For more information, see Table 34.
Per-queue output statistics	Yes	No	Yes	Yes	Per-queue output statistics are shown in the output of the show interfaces queue command.
Rewrite Markers
Maximum number per FPC, PIC, or PIM	64	No maximum	No maximum	64	–
dscp	Yes	No	Yes	Yes	For J-series PIMs and M-series Enhanced FPC, bits 0 through 5 are rewritten, and bits 6 through 7 are preserved. For M320 and T-series non-IQ FPCs, bits 0 through 5 are rewritten, and bits 6 through 7 are preserved. For M320 and T-series FPCs, you must decode the loss priority using the firewall filter before you can use loss priority to select the rewrite CoS value. For more information, see Setting the PLP on T320 and M320 Platforms. For M320 and T-series FPCs, Adaptive Services PIC link services IQ interfaces (lsq-) do not support DSCP rewrite markers.
dscp-ipv6	Yes	No	Yes	Yes	For J-series PIMs, M-series Enhanced FPC, and M320 and T-series FPCs, bits 0 through 5 are rewritten, and bits 6 through 7 are preserved. For M320 and T-series FPCs, you must decode the loss priority using the firewall filter before you can use loss priority to select the rewrite CoS value. For more information, see Setting the PLP on T320 and M320 Platforms. For M320 and T-series FPCs, Adaptive Services PIC link services IQ interfaces (lsq-) do not support DSCP rewrite markers.
frame-relay-de	Yes	No	No	No	–
ieee-802.1	Yes	No	Yes	Yes	For M-series enhanced FPCs and T-series FPCs, fixed rewrite loss priority determines the value for bit 0; queue number (forwarding class) determines bits 1 and 2. For IQ PICs, you can only configure one IEEE 802.1 rewrite rule on a physical port. All logical ports (units) on that physical port should apply the same IEEE 802.1 rewrite rule.
inet-precedence	Yes	Yes	Yes	Yes	For J-series PIMs, bits 0 through 2 are rewritten, and bits 3 through 7 are preserved. For M-series FPC, bits 0 through 2 are rewritten, and bits 3 through 7 are preserved. For M-series Enhanced, bits 0 through 2 are rewritten, bits 3 through 5 are cleared, and bits 6 through 7 are preserved. For M320 and T-series FPCs, bits 0 through 2 are rewritten and bits 3 through 7 are preserved. For M320 and T-series FPCs, you must decode the loss priority using the firewall filter before you can use loss priority to select the rewrite CoS value. For more information, see Setting the PLP on T320 and M320 Platforms.
mpls-exp	Yes	Yes	Yes	Yes	For M320 and T-series FPCs, you must decode the loss priority using the firewall filter before you can use loss priority to select the rewrite CoS value. For more information, see Setting the PLP on T320 and M320 Platforms. For M-series FPCs, fixed rewrite loss priority determines the value for bit 0; queue number (forwarding class) determines bits 1 and 2.

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