Configuring Large Delay Buffers for Slower Interfaces

By default, T1, E1, and NxDS0 interfaces and DLCIs configured on channelized IQ PICs are limited to 100,000 microseconds of delay buffer. (The default average packet size on the IQ PIC is 40 bytes.) For these interfaces, it might be necessary to configure a larger buffer size to prevent congestion and packet dropping. You can do so on the following PICs:

• Channelized IQ
• 4-port E3 IQ
• Gigabit Ethernet IQ and IQ2

Congestion and packet dropping occur when large bursts of traffic are received by slower interfaces. This happens when faster interfaces pass traffic to slower interfaces, which is often the case when edge devices receive traffic from the core of the network. For example, a 100,000-microsecond T1 delay buffer can absorb only 20 percent of a 5000-microsecond burst of traffic from an upstream OC3 interface. In this case, 80 percent of the burst traffic is dropped.

Table 30 shows some recommended buffer sizes needed to absorb typical burst sizes from various upstream interface types.

Table 30: Recommended Delay Buffer Sizes

To ensure that traffic is queued and transmitted properly on E1, T1, and NxDS0 interfaces and DLCIs, you can configure a buffer size larger than the default maximum. To enable larger buffer sizes to be configured, include the q-pic-large-buffer (large-scale | small-scale) statement at the [edit chassis fpc slot-number pic pic-number] hierarchy level:

If you specify large-scale, the feature supports a larger number of interfaces. If you specify small-scale, the default, then the feature supports a smaller number of interfaces.

When you include the q-pic-large-buffer statement in the configuration, the larger buffer is transparently available for allocation to scheduler queues. The larger buffer maximum varies by interface type, as shown in Table 31.

Table 31: Maximum Delay Buffer with q-pic-large-buffer Enabled by Interface

If you configure a delay buffer larger than the new maximum, the candidate configuration can be committed successfully. However, the setting is rejected by the packet forwarding component, the default setting is used instead, and a system log warning message is generated.

For interfaces that support DLCI queuing, the large buffer is supported for DLCIs on which the configured shaping rate is less than or equal to the physical interface bandwidth. For instance, when you configure a Frame Relay DLCI on a Channelized T3 IQ PIC, and you configure the shaping rate to be 1.5 Mbps, the amount of delay buffer that can be allocated to the DLCI is 500,000 microseconds, which is equivalent to a T1 delay buffer. For more information about DLCI queuing, see Associating the Scheduler Map and a Shaping Rate with a DLCI or VLAN.

For NxDS0 interfaces, the larger buffer sizes can be up to 4,000,000 microseconds, depending on the number of DS0 channels in the NxDS0 interface. For slower NxDS0 interfaces with fewer channels, the delay buffer can be relatively larger than for faster NxDS0 interfaces with more channels. This is shown in Table 33. To calculate specific buffer sizes for various NxDS0 interfaces, see Maximum Delay Buffer for NxDS0 Interfaces.

You can allocate the delay buffer as either a percentage or a temporal value. The resulting delay buffer is calculated differently depending how you configure the delay buffer, as shown in Table 32.

Table 32: Delay-Buffer Calculations

For more information, see the following sections:

• Maximum Delay Buffer for NxDS0 Interfaces
• Example: Configuring Large Delay Buffers for Slower Interfaces

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