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M13 Asynchronous
Framing
A DS3 M-frame includes seven subframes, formed by DS2 data bits
interleaved from the seven multiplexed DS2 signals. Each subframe
has eight 85-bit blocks—a DS3 OH bit plus 84 data bits. The
meaning of an OH bit depends on the block it precedes. Standard DS3
M13 asynchronous framing format is shown in Figure 3.
Figure 3: DS3 M13 Frame Format
A DS3 M13 M-frame contains the following types of OH bits:
- Framing bits (F-bits)—Make up a frame alignment
signal that synchronizes DS3 subframes. Each DS3 frame contains 28 F-bits
(4 bits per subframe). F-bits are located at the beginning of
blocks 2, 4, 6, and 8 of each subframe. When combined, the frame alignment
pattern for each subframe is 1001. The pattern can be examined to
detect bit errors in the transmission.
- Multiframing bits (M-bits)—Make up a multiframe
alignment signal that synchronizes the M-frames in a DS3 signal. Each
DS3 frame contains 3 M-bits, which are located at the beginning
of subframes 5, 6, and 7. When combined, the multiframe alignment
patter for each M-frame is 010.
- Bit stuffing control bits (C-bits)—Serve as bit
stuffing indicators for each DS2 input. For example, C11, C12, and C13 are
indicators for DS2 input 1. Their values indicate whether DS3
bit stuffing has occurred at the multiplexer. If the three C-bits
in a subframe are all 0s, no stuffing was performed for the DS2 input.
If the three C-bits are all 1s, stuffing was performed.
- Message bits (X-bits)—Used by DS3 transmitters to
embed asynchronous in-service messages in the data transmission. Each
DS3 frame contains 2 X-bits, which are located at the beginning
of subframes 1 and 2. Within an DS3 M-frame, both X-bits must be identical.
- Parity bits (P-bits)—Compute parity over all but
1 bit of the M-frame. (The first X-bit is not included.) Each
DS3 frame contains 2 P-bits, which are located at the beginning
of subframes 3 and 4. Both P-bits must be identical.
If the previous DS3 frame contained an odd number of 1s, both
P-bits are set to 1. If the previous DS3 contained an even number
of 1s, both P-bits are set to 0. If, on the receiving side, the number
of 1s for a given frame does not match the P-bits in the following
frame, it indicates one or more bit errors in the transmission.
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