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Table of Contents

Channelized IQ Interfaces

Channelized Intelligent Queuing Interfaces Concepts and Reference Material

Overview of Channelized IQ Interfaces
Guidelines for Configuring Channelized IQ Interfaces
Frame Relay DLCI Limitations for Channelized IQ Interfaces
System Requirements for Channelized IQ Interfaces
Terms and Acronyms for Channelized IQ Interfaces

Configuring Channelized IQ Interfaces

Roadmap for Configuring Channelized IQ Interfaces

Configuring a Clear Channel on a Channelized IQ Interface

Configuring Single-Level Channels on a Channelized IQ Interface

Configuring Multilevel Channels on a Channelized IQ Interface

Configuring Class of Service on a Channelized IQ Interface

Configuring a Class-of-Service Scheduler Map
Associating the Scheduler with a DLCI on a Channelized IQ Interface
Scheduler Limitations for Channelized IQ Interfaces
Verifying Class-of-Service Schedulers on Channelized IQ Interfaces

Channelized IQ Interface Configuration Examples

Merging Examples

Roadmap for Channelized IQ Interface Configuration Examples

Example: OC12 Clear Channel on a Channelized OC12 IQ Interface

Verifying Your Work

Example: Complex Configuration for a Channelized OC12 IQ Interface

Verifying Your Work

Channelized OC12
SONET OC3
T3
Channelized T3
Channelized OC1
Channelized T1
T1
DS0

Example: Converting a Channelized OC12 IQ PIC to a Channelized STM4 IQ Interface

Verifying Your Configuration

Example: Channelized OC3 IQ Interface Configuration

Verifying Your Work

Channelized OC3
Channelized OC1
T3
Channelized T3
T1
Channelized T1
NxDS0
Clear Channel SONET OC3

Example: Channelized DS3 IQ Interface Configuration

Verifying Your Work

Example: Channelized T1 IQ Interface Configuration

Verifying Your Work

Example: Channelized STM1 IQ Interface Configuration

Verifying Your Work

Example: Channelized E1 IQ Interface Configuration

Verifying Your Work

Example: DLCI Class of Service on a Channelized IQ Interface Configuration

Verifying Your Work

Index

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