Data Flow Through the M160 Router Packet Forwarding Engine

Data flows through the M160 router Packet Forwarding Engine in the sequence shown in Figure 19.

Figure 19: M160 Router Packet Forwarding Engine Components and Data Flow

1. Packets arrive at an incoming PIC interface.
2. The PIC passes the packets to the FPC, where the Packet Director ASIC distributes them among the I/O Manager ASICs.
3. The I/O Manager ASICs process the packet headers, divide the packets into 64-byte data cells, and pass the cells through the midplane to the SFMs.
4. The Distributed Buffer Manager ASICs on the SFMs distribute the data cells throughout memory buffers located on and shared by all the FPCs.
5. For each packet, an Internet Processor II ASIC on an SFM performs a route lookup and decides how to forward the packet.
6. The Internet Processor II ASIC notifies a second Distributed Buffer Manager ASIC (on the SFM) of the forwarding decision, and the Distributed Buffer Manager ASIC forwards the notification to the FPC that hosts the appropriate outbound interface.
7. The I/O Manager ASIC on the FPC reassembles data cells in shared memory into data packets as they are ready for transmission and passes them through the Packet Director ASIC to the outbound PIC.
8. The outbound PIC transmits the data packets.