Clocking Features

All Circuit Emulation PICs support the following features:

• External clocking—Also known as “loop timing”. Clock is distributed via the TDM interfaces.
• Internal clocking with external synchronization—Also known as “external timing” or “external synchronization”.
• Adaptive clock recovery—Our proprietary method of recovering a clock, based on the arrival rate of packets. The accuracy of the recovered clock depends on the packet delay variation. This method of clock recovery is also known as “circuit emulation system” clocking.
• Internal clocking with FPC-based synchronization—Synchronizing the internal clock with a clock supplied by each FPC to the timing module is an alternative to external synchronization. The following are potential sources for FPC-supplied clock:
  • Clock recovered from TDM interface – also called “line timing” or “line synchronization (system level)”
  • Clock recovered from CES (adaptive clock recovery)
  • Clock recovered from IEEE 1588v2
• Internal clocking with PIC-level line synchronization—Synchronizing the PIC’s internal clock with a clock recovered from a TDM interface local to the PIC-provided line timing at the PIC level.

This feature set is useful for aggregation in mobile backhaul applications.

Note: The PRS of the clock recovered from one interface may not be the same as that of another TDM interface. There is a limitation on the number of timing domains that can be supported in practice.

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