Clock Sources on Channelized Interfaces

Channelized interfaces and channelized IQ and IQE interfaces have different clocking capabilities. For channelized IQ and IQE interfaces, you can configure clocking on each interface independently by including the clocking (internal | external) statement at the [edit interfaces interface-name] hierarchy level.

For channelized IQ and IQE interfaces, clocking is provided as follows:

• For all channelized IQ and IQE PICs, the clocking statement is supported on all channels. To configure SONET/SDH or DS3-level clocking, include the loop-timing statement at the [edit interfaces cstm1-fpc/pic/port sonet-options] or [edit interfaces ct3-fpc/pic/port t3-options] hierarchy level. To configure clocking on individual interfaces, include the clocking statement at the [edit interfaces type-fpc/pic/port:channel] hierarchy level. If you do not include the clocking statement, the individual interfaces use internal clocking by default.
• SONET/SDH-level clocking is provided at the [edit interfaces coc3-fpc/pic/port], [edit interfaces coc12-fpc/pic/port], and [edit interfaces cstm1-fpc/pic/port] hierarchy levels.
• Configure T3-level clocking by including the loop-timing statement at the [edit interfaces ct3-fpc/pic/port t3-options] hierarchy level.
• Configure T1-level clocking by including the clocking statement at the [edit interfaces t1-fpc/pic/port:channel] hierarchy level.
• Configure E1-level clocking by including the clocking statement at the [edit interfaces ce1-fpc/pic/port] hierarchy level.
• Configure clocking for all NxDS0 channels by including the clocking statement at the [edit interfaces ct1-fpc/pic/port:channel] or [edit interfaces ce1-fpc/pic/port] hierarchy level.
• The clocking statement is ignored if you include it at the [edit interfaces coc1-fpc/pic/port:channel] or [edit interfaces cau4-fpc/pic/port:channel] hierarchy level.
• If you include the clocking statement at both the channelized and interface levels—[edit interfaces coc12-fpc/pic/port] and [edit interfaces so-fpc/pic/port], for example—the clocking configuration at the channelized level ([edit interfaces coc12-fpc/pic/port] in this example) takes precedence.

For non-IQ and non-IQE channelized interfaces, clocking at each channel level is provided as follows:

• For Channelized OC12, DS3, and E1 PICs, the clocking statement is supported only for channel 0; it is ignored if included in the configuration of other channels. The clock source configured for channel 0 applies to all channels on these channelized interfaces.
• For the Channelized STM1 PIC, the clocking statement is supported on channels 0 through 62. To configure clocking on the STM1 interface, include the loop-timing statement at the [edit interfaces e1-fpc/pic/port :0 sonet-options] hierarchy level. To configure clocking on individual E1 interfaces, include the clocking statement at the [edit interfaces e1-fpc/pic/port:channel] hierarchy level. The channel number can be 0 through 62. If you do not include the clocking statement, the individual E1 interfaces use internal clocking by default.
• For channelized STM1 interfaces, you should configure the clock source at one side of the connection to be internal and configure the other side of the connection to be external.
• When you configure the clock source for a channelized interface—t3-fpc/pic/port:0, for example—you must also include the channel-group statement at the [edit chassis] hierarchy level, and specify channel group 0.

Table 37 lists the clocking capabilities for each channelized PIC.

Table 37: Clocking Capabilities by Channelized PIC Type

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