Channelized OC12 Overview

Channelized intelligent queuing (IQ) interfaces allow arbitrary and dynamic channelization of serial links, allowing greater flexibility than the channelized interfaces. Figure 34, Figure 35, and Figure 36 illustrate the difference in flexibility between Channelized OC12 IQ or IQE Physical Interface Cards (PICs) and a channelized OC12 PIC.

Figure 34: Sample Channelization of OC12 IQ or IQE PIC (SONET Mode)

In Figure 34, a Channelized OC12 IQ or IQE PIC operating in SONET mode is partitioned into the following OC slices:

1. An OC3 interface
2. Another OC3 interface
3. A channelized OC1 partitioned into T1 interfaces
4. A channelized OC1 converted into a T3 interface
5. A channelized OC1 partitioned into T1 interfaces and channelized T1s, which are partitioned into NxDS0 interfaces
6. A channelized OC1 converted into a channelized T3, which is partitioned into T1 interfaces
7. A channelized OC1 converted into a channelized T3, which is partitioned into T1 interfaces and a channelized T1, which is partitioned into NxDS0 interfaces
8. A channelized OC1 partitioned into channelized T1s, which are partitioned into NxDS0 interfaces

This is one of thousands of ways to configure a Channelized OC12 IQ or IQE PIC. To configure the interfaces shown in Figure 34, see Example: Configuring Channelized OC12 IQ Interfaces.

Figure 35: Sample Channelization of OC12 IQ or IQE PIC (SDH Mode)

In Figure 35, a Channelized OC12 IQ or IQE PIC operating in SDH mode results in a channelized STM4 interface, which can be nonpartitioned into one SDH VC-4-VC interface or partitioned into the following OC slices:

1. An SDH VC-4 interface.
2. A channelized administrative unit 4 (AU-4) partitioned into channelized T3 interfaces and T3 interfaces.
3. Another channelized AU-4 interface converted into T3 interfaces.
4. Another channelized AU-4 interface converted into a channelized T3 interface, which is partitioned further into a channelized T1 and a T1 interface. The channelized T1 interface is further partitioned into NxDS0 interfaces.

This is one of thousands of ways to configure a Channelized OC12 IQ or IQE PIC.

Figure 36: Sample Channelization of OC12 PIC

Figure 36 shows five T3 channels configured on the Channelized OC12 PIC. You can configure seven additional T3 channels. For more information about configuring Channelized OC12 PICs, see Configuring Channelized OC12 Interfaces.

For a full configuration example, see the JUNOS Feature Guide.

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