Channelized IQ and IQE Interfaces Properties

On channelized IQ and IQE interfaces, you can specify options that are globally applied to all interface types associated with channelized IQ and IQE interfaces. For example, e1-options statements that you include at the [edit interfaces ce1-fpc/pic/port ] hierarchy level apply globally to all E1 and NxDS0 interfaces that you create by partitioning ce1-fpc/pic/port. Likewise, t3-options statements that you include at the [edit interfaces ct3-fpc/pic/port ] hierarchy level apply globally to all T1 and NxDS0 interfaces that you create by partitioning ct3-fpc/pic/port.

You can also apply interface options at the channel level. For example, you can include t1-options statements at the [edit interfaces t1-fpc/pic/port <:channel>] hierarchy level, and ds0-options statements at the [edit interfaces ds-0/1/1<:channel>] hierarchy level.

Only a subset of the interface options is valid on each type of channelized IQ interface. You configure all HDLC information at the end-data channel level, not at the parent level. For example, configure HDLC information at the [edit interfaces ds-fpc/pic/port<:channel>] hierarchy level, not at the [edit interfaces ct1-fpc/pic/port<:channel>] hierarchy level.

Automatic Protection Switching (APS) is supported on channelized STM1 IQ interfaces and channelized OC12 IQ interfaces. To configure APS, include the aps statement with options at the [edit interfaces interface-name sonet-options] hierarchy level. For information about configuring APS, see Configuring APS and MSP.

In interchassis and intrachassis redundant LSQ configurations that use MLPPP and SONET APS, you can inhibit a router from sending PPP termination-request messages to the remote host if the link PIC fails. To inhibit the router from sending PPP termination-request messages to the remote host if the link PIC fails, include the no-termination-request statement at the [edit interfaces interface-name ppp-options] hierarchy level.

The no-termination-request statement is supported only with MLPPP and SONET APS configurations and works with PPP, PPP over Frame Relay, and MLPPP interfaces only. The supported PIC types are as follows:

• Channelized OC3 IQ and IQE PICs
• Channelized OC12 IQ and IQE PICs
• Channelized STM1 IQ and IQE PICs
• Channelized STM4 IQ and IQE PICs

Channelized IQ and IQE interfaces do not support receive buckets or transmit buckets.

For channelized IQ and IQE interfaces, there are some limitations on where you place certain statements in the configuration. When you configure clocking, bit error rate testing (BERT), C-bit parity, and loopback statements on T3, T1, or DS0 channels, you must follow these guidelines:

• For T3 IQ interfaces, you can include the loopback payload statement at the [edit interfaces ct3-fpc/pic/port] and [edit interfaces t3-fpc/pic/port:channel] hierarchy levels. For T1 interfaces, you can include the loopback payload statement at the [edit interfaces t1-fpc/pic/port:channel] hierarchy level; it is ignored if included at the [edit interfaces ct1-fpc/pic/port] hierarchy level. For NxDS0 interfaces, payload and remote loopback are the same. If you configure one, the other is ignored. NxDS0 IQ interfaces do not support local loopback.
• If you include clocking, BERT, and C-bit parity configurations at both the [edit interfaces ct3-fpc/pic/port<:channel> t3-options] and [edit interfaces t3-fpc/pic/port<:channel> t3-options] hierarchy levels, the channelized T3-level statements are valid, and the T3-level statements are ignored.
• If you include clocking, BERT, and C-bit parity configurations at both the [edit interfaces ct3-fpc/pic/port<:channel> t3-options] and [edit interfaces t1-fpc/pic/port<:channel> t1-options] hierarchy levels, the channelized T3-level statements are operational for the T3 connections and the T1-level statements are operational for the T1 connections.
• Because DS0 channels do not have clocking capability, you must configure clocking at the [edit interfaces ct1-fpc/pic/port<:channel> t1-options] or [edit interfaces ce1-fpc/pic/port<:channel> e1-options] hierarchy level for channelized NxDS0 IQ interfaces.
• You can set BERT at the [edit interfaces t3-fpc/pic/port<:channel> t3-options] hierarchy level or on any partitioned channel of the channelized T3 interface. There are twelve BERT patterns available for NxDS0 channels and twenty-eight BERT patterns for T1, channelized T1, T3, and channelized T3 interfaces within channelized IQ interfaces.
• For channelized interfaces that use Frame Relay encapsulation, the number of configurable DLCIs varies by channelized interface type.
• For channelized interfaces, you can configure class of service (CoS) on channels, but not at the controller level.
• For original Channelized OC12 PICs, limited CoS functionality is supported. For more information, contact Juniper Networks customer support.
• CoS is not configurable on the following channelized interfaces:
  • cau4—Channelized STM1 IQ interface (configured on the Channelized STM1 IQ and IQE PICs).
  • coc1—Channelized OC1 IQ interface (configured on the Channelized OC12 IQ and IQE PICs).
  • coc12—Channelized OC12 IQ interface (configured on the Channelized OC12 IQ and IQE PICs).
  • cstm1—Channelized STM1 IQ interface (configured on the Channelized STM1 IQ and IQE PICs).
  • ct1—Channelized T1 IQ interface (configured on the Channelized DS3 IQ and IQE PIC or Channelized OC12 IQ and IQE PICs).
  • ct3—Channelized T3 IQ interface (configured on the Channelized DS3 IQ and IQE PICs or Channelized OC12 IQ and IQE PICs).
  • ce1—Channelized E1 IQ interface (configured on the Channelized E1 IQ and IQE PICs or Channelized STM1 IQ and IQE PICs).

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