The fundamental flow of a packet subjected to CoS is different in the MX-series with integrated chips than it is in the M- and T-series routers, which have a different packet handling architecture.
The way that a packet makes its way through an M- or T-series router with IQ2 PICs is shown in Figure 15. Note that the per-VLAN scheduling and shaping are done on the PIC while all other CoS functions at the port level are performed on the Packet Forwarding Engine.
Figure 15: Packet Handling on the M- and T-series Routers
The way that a packet makes its way through an MX-series router with Enhanced Queuing DPCs is shown in Figure 16. Note that the scheduling and shaping are done with an integrated architecture on the DPC along with all other CoS functions. In particular, scheduling and shaping are done on the Ethernet services engine network processing unit (ESE NPU). Hierarchical scheduling is supported on the output side only.
Figure 16: Packet Handling on the MX-series Routers
 | Copyright © 2008, Juniper Networks, Inc. All rights reserved. Trademark Notice. | |