Overview

Channelized interfaces allow service providers to customize bandwidth to satisfy the needs of their customers. Whether the subscriber needs DS0, T1, fractional T1, E1, fractional E1, T3, STM1, OC3, or OC12 service, a channelized interface can provide the necessary bandwidth today and can be reconfigured to support the customer’s expanding network tomorrow. Standard channelized interfaces have been available on Juniper Networks routing platforms since JUNOS Release 3.4. These original channelized interfaces for Juniper Networks M-series routers are available in the following models:

• 1-port Channelized OC12 PIC
• 10-port Channelized E1 PIC
• 1-port Channelized STM1 PIC
• 4-port Channelized DS3 PIC
• 1-port and 2-port multichannel Channelized DS3 PIC

These original channelized interfaces provide a single level of channelization and require configuration at both the [edit chassis] and the [edit interfaces] hierarchy levels. Most configuration options must be set on channel 0 and they apply to all channels on these channelized interfaces.

The new channelized interfaces with intelligent queuing offer several advantages over the original channelized interfaces:

• Complete configuration tasks for channelized IQ interfaces are now centralized at the [edit interfaces] hierarchy level.
• Multiple levels of channelization are now possible with channelized IQ interfaces. For example, a channelized OC12 IQ interface can be divided into channelized OC1 interfaces, then subdivided into channelized T1 interfaces, and further split into NxDS0 channels.
• You can now configure interface statements, such as clocking, on individual channels rather than configuring them on channel 0 for all channels at the same hierarchy level.
• Class-of-service (CoS) processing now occurs on the PIC for channelized IQ interfaces rather than in the FPC.

The following M-series and T-series PICs support channelized interfaces with intelligent queuing:

• 1-port Channelized OC12 IQ PIC
• 1-port Channelized OC3 PIC
• 4-port Channelized DS3 IQ PIC
• 10-port Channelized T1 IQ PIC
• 10-port Channelized E1 IQ PIC
• 1-port Channelized STM1 IQ PIC

To determine which PIC is installed, issue the show chassis hardware command:

Hardware inventory:
Item             Version  Part number  Serial number     Description
Chassis                                20070             M160
Midplane         REV 03   710-001245   AB4123           
FPM CMB          REV 02   710-001642   AB3266           
FPM Display      REV 02   710-001647   AB3038           
CIP              REV 04   710-001593   AB3276           
PEM 0            Rev 03   740-001243   KM28410           DC
PEM 1            Rev 03   740-001243   LF21558           Power Entry Module
PCG 0            REV 03   710-001568   AB3006           
PCG 1            REV 02   710-001568   AB2992           
Routing Engine 0                       20000005dfae3a01  RE-2.0
MCS 0            REV 04   710-001226   AB3208           
MCS 1            REV 04   710-001226   AB3212           
SFM 0 SPP        REV 06   710-001228   AB3103           
SFM 0 SPR        REV 01   710-002189   AB2936            Internet Processor II
SFM 1 SPP        REV 07   710-001228   AG2634           
SFM 1 SPR        REV 03   710-002189   AE3503            Internet Processor II
SFM 2 SPP        REV 06   710-001228   AB2976           
SFM 2 SPR        REV 01   710-002189   AB2938            Internet Processor II
SFM 3 SPP        REV 06   710-001228   AB5826           
SFM 3 SPR        REV 01   710-002189   AB2917            Internet Processor II
FPC 0            REV 03   710-003947   HE0614            E-FPC Type 1
  CPU            REV 01   710-004600   AT3217           
  PIC 0          REV 03   750-005636   BE1826            4x CHDS3 IQ

  PIC 1          REV 07   750-003846   HG5572            1x 800M Crypto
  PIC 2          REV 01   750-004507   BA5341            10x CE1-NxDS0
  PIC 3          REV 06   750-003009   AM6929            4x CT3

FPC 1            REV 03   710-003309   AD9434            E-FPC Type 2
  CPU            REV 05   710-001217   AH2707           
  PIC 2          REV 05   750-001900   AD5738            1x OC-48 SONET, SMSR
  PIC 3          REV 04   750-003737   BC1106            4x G/E, 1000 BASE-SX

When you configure channelized IQ interfaces, keep in mind these rules of thumb:

• You normally configure media-related statements and options at the physical interface level (also known as the controller level). This level is indicated by the [edit interfaces cxx-fpc/pic/port] hierarchy level.
• You should always configure HDLC-related statements (for example, bytes, fcs, idle-cycle-flag, mtu, receive-bucket, start-end-flag, and transmit-bucket) and logical interfaces (for example, [edit interfaces interface-name unit unit-number]) on end channels such as DS0 and T1. Never configure these statements at the controller level.
• Pay attention to the channel numbering rules:
  • OC3 data channels configured on channelized OC12 IQ interfaces are numbered from 1 to 4.
  • T3 channels configured on a channelized OC12 IQ or channelized OC3 IQ interface are numbered from 1 to 12.
  • T1 channels on a channelized OC12 IQ, channelized OC3 IQ, channelized DS3 IQ, or channelized T1 IQ interface are numbered from 1 to 28.
  • E1 channels configured on a channelized STM1 IQ interface are numbered from 1 to 63.
  • NxDS0 time slots configured on a channelized OC12 IQ, channelized OC3 IQ, channelized DS3 IQ, or channelized T1 IQ interface are numbered from 1 to 24.
  • NxDS0 time slots configured on either a channelized STM1 IQ interface or channelized E1 IQ interface are numbered from 2 to 32 (1 is reserved).
• You can configure Automatic Protection Switching (APS) on channelized OC12 IQ interfaces and Multiplex Section Protection (MSP) on channelized STM1 IQ interfaces. The JUNOS implementation of APS and MSP allows you to protect against circuit failures between a SONET/SDH add/drop multiplexer (ADM) and one or more routers, and between multiple interfaces in the same router. When a device fails, a backup device immediately takes over.

  You configure APS and MSP at the controller level only. To configure, include the working-circuit and protect-circuit statements at the [edit interfaces coc12-fpc/pic/port sonet-options aps] or [edit interfaces coc3-fpc/pic/port sonet-options aps] hierarchy level for APS and the [edit interfaces cstm1-fpc/pic/port sonet-options aps] hierarchy level for MSP.

  When you enable the controller-level interface as the working circuit, all partitions under the working circuit are also enabled. This is the default behavior even when APS or MSP is not configured. When the backup circuit interface is disabled, all partitions under this protected circuit are also disabled. If the working circuit fails, the interfaces are switched: The working circuit and all its partitions are disabled, and the protect circuit and all its partitions are enabled. You can verify this behavior by entering the show interfaces controller command. The disabled interfaces are shown as “admin down” and the enabled interfaces are shown as “admin up.”

• You can delete several channelized interfaces simultaneously by using a single command and regular expressions. To delete sequential channelized interfaces, issue the wildcard command with the delete option at the [edit] hierarchy level. Specify the hierarchy level and the channelized interfaces to be summarized with a regular expression. For example, to delete channelized interfaces in the range of ds-0/0/0:0:0 through ds-0/0/0:0:23, issue the command:

  user@router# wildcard delete interfaces ds-0/0/0:0:.*

• If you use Frame Relay encapsulation on a channelized interface, see Table 7 for the maximum number of data-link connection identifiers (DLCIs) per channel that you can configure at each channel level for various channelized PICs.

  Note: The actual number of DLCIs you can configure for each channel is determined by the capabilities of your system, such as the number and type of PICs installed. If the number of DLCIs in the configuration exceeds the capabilities of your system, the router might not be able to support the maximum DLCI values shown in Table 7. To determine the capabilities of your system, contact Juniper Networks customer support.

Table 7: Frame Relay DLCI Limitations for Channelized Interfaces

• In JUNOS Release 6.2 and later, additional Frame Relay encapsulation types on physical interfaces and channels of channelized IQ interfaces are available:
  • Extended Frame Relay CCC—Allows you to assign any DLCI number from 1 to 1022 on Frame Relay CCC logical interfaces. To configure, include the extended-frame-relay-ccc statement at the [edit interfaces interface-name encapsulation] hierarchy level.
  • Extended Frame Relay TCC—Allows you to assign any DLCI number from 1 to 1022 on Frame Relay TCC logical interfaces. To configure, include the extended-frame-relay-tcc statement at the [edit interfaces interface-name encapsulation] hierarchy level.
  • Flexible Frame Relay—Allows you to configure any DLCI number from 1 to 1022 and any combination of Frame Relay encapsulation types on logical interfaces. To configure, include the flexible-frame-relay statement at the [edit interfaces interface-name encapsulation] hierarchy level.
• When you configure clocking, bit error rate testing (BERT), C-bit parity, and loopback statements on T3, T1, or DS0 channels on channelized IQ interfaces, you must follow these guidelines:
  • If you include the statements at both the [edit interfaces ct3-fpc /pic/\port:channel t3-options] and [edit interfaces t3-fpc/pic/port:channel t3-options] hierarchy levels, channelized T3-level statements are operational and T3-level statements are ignored.
  • If you include the statements at both the [edit interfaces ct3-fpc/pic/port:channel t3-options] and [edit interfaces t1-fpc/pic/port:channel t1-options] hierarchy levels, the channelized T3-level statements are operational for the T3 connections and the T1-level statements are operational for the T1 connections.
  • Because DS0 channels do not have a valid clocking option, you must configure clocking for all NxDS0s at the [edit interfaces ct1-fpc/ pic/port:channelt1-options] hierarchy level.
  • You configure BERT at the [edit interfaces ct3-fpc/pic/port:channel t3-options] hierarchy level or on any partitioned subchannel of the channelized T3 interface. There are 12 BERT patterns available for DS0 channels and 28 BERT patterns for T1, channelized T1, T3, and channelized T3 channels within channelized IQ interfaces.
  • For Channelized OC3 IQ PICs, if you need a remote loopback on a far-end NxDS0 interface, and you are running a BERT test from the local NxDS0 interface, you must configure a remote loopback on the associated channelized T1 interface (ct1) for the far-end routing platform. To do this, include the loopback remote statement at the [edit interfaces ct1-fpc/pic/port t1-options] hierarchy level.
  • You can configure loopbacks at the [edit interfaces ct3-fpc/pic/port:channel t3-options] hierarchy level. Local loopbacks recirculate framing information within the local router. Remote loopbacks resend entire frames back to the remote sender. A new loopback called a payload loopback is similar to a remote loopback, but it resends only the data portion of a frame back to the remote sender.
  • You can configure C-bit parity at the [edit interfaces ct3-fpc/ pic/port:channel t3-options]hierarchy level or on any partitioned subchannel of the channelized T3 interface.
• In JUNOS Release 7.5 and later, you can increase the delay buffer for E1, T1, and NxDS0 channels on all Channelized IQ PICs (except the Channelized OC12 IQ PIC) by including the q-pic-large-buffer statement at the [edit chassis fpc fpc-slot pic pic-slot] hierarchy level. By doing so, you enable the slower interfaces to handle bursts of traffic from faster upstream neighbors. As a result, any class-of-service (CoS) scheduler that you apply to an interface will inherit the larger delay buffer and the buffer is shared across all four CoS queues. For more information about increasing the delay buffer, see the JUNOS Class of Service Configuration Guide.

Note: If you configure the q-pic-large-buffer statement and APS in a multirouter topology, the Channelized IQ PIC resets and causes an APS switchover.

For more details on channelized interface options, see the JUNOS Network Interfaces Configuration Guide.

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