Data Flow Through the M5 and M10 Router Packet Forwarding Engine

Data flows through the M5 and M10 router Packet Forwarding Engine in the sequence shown in Figure 13:

Figure 13: M5 and M10 Router Packet Forwarding Engine Components and Data Flow

1. Packets arrive at an incoming PIC interface.
2. The PIC passes the packets through the midplane to the FEB, where the I/O Manager ASIC breaks them into 64-byte cells.
3. The Distributed Buffer Manager ASIC on the FEB distributes the data cells throughout memory banks on the FEB.
4. The Internet Processor II ASIC on the FEB performs route lookups and makes forwarding decisions.
5. The Internet Processor II ASIC notifies a second Distributed Buffer Manager ASIC on the FEB, which forwards the notification to the outgoing interface.
6. The I/O Manager ASIC on the FEB reassembles data cells in shared memory into data packets as they are ready for transmission and passes them to the outgoing PIC through the midplane.
7. The outgoing PIC transmits the data packets.